Update FSP to follow:
https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf
Clean update API definition to align with FSP2.0.
Clean up Null library instance.
Cc: Giri P Mudusuru <giri.p.mudus...@intel.com>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Ravi P Rangarajan <ravi.p.rangara...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen....@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudus...@intel.com>
Reviewed-by: Maurice Ma <maurice...@intel.com>
Reviewed-by: Ravi P Rangarajan <ravi.p.rangara...@intel.com>
---
IntelFspPkg/Include/Library/FspSecPlatformLib.h | 10 +--
IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.asm | 76
++++----------------
IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.s | 71
++----------------
IntelFspPkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c | 5 +-
4 files changed, 24 insertions(+), 138 deletions(-)
diff --git a/IntelFspPkg/Include/Library/FspSecPlatformLib.h
b/IntelFspPkg/Include/Library/FspSecPlatformLib.h
index d5c7e77..cf2b0ff 100644
--- a/IntelFspPkg/Include/Library/FspSecPlatformLib.h
+++ b/IntelFspPkg/Include/Library/FspSecPlatformLib.h
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -41,7 +41,7 @@ SecPlatformInit (
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
- @param TempRamInitParamPtr A data structure to hold microcode parameter. It
is saved in ESP.
+ @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data
structure. It is saved in ESP.
@retval in saved in EAX - 0 means Microcode is loaded successfully.
other means Microcode is not loaded successfully.
@@ -49,7 +49,7 @@ SecPlatformInit (
UINT32
EFIAPI
LoadMicrocode (
- IN FSP_TEMP_RAM_INIT_PARAMS *TempRamInitParamPtr
+ IN VOID *FsptUpdDataPtr
);
/**
@@ -60,7 +60,7 @@ LoadMicrocode (
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
- @param TempRamInitParamPtr A data structure to hold microcode parameter. It
is saved in ESP.
+ @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data
structure. It is saved in ESP.
@retval in saved in EAX - 0 means CAR initialization success.
other means CAR initialization fail.
@@ -68,7 +68,7 @@ LoadMicrocode (
UINT32
EFIAPI
SecCarInit (
- IN FSP_TEMP_RAM_INIT_PARAMS *TempRamInitParamPtr
+ IN VOID *FsptUpdDataPtr
);
/**
diff --git a/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.asm
b/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.asm
index 391fdf8..9f144fc 100644
--- a/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.asm
+++ b/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.asm
@@ -2,7 +2,7 @@
; This is the code that goes from real-mode to protected mode.
; It consumes the reset vector, configures the stack.
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD
License
; which accompanies this distribution. The full text of the license may be
found at
@@ -20,76 +20,25 @@
.model flat, c
EXTRN TempRamInitApi:NEAR
-EXTRN FspInitApi:NEAR
-;
-; Contrary to the name, this file contains 16 bit code as well.
-;
-_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
- ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
+.code
-;----------------------------------------------------------------------------
-;
-; Procedure: _ModuleEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; Transition to non-paged flat-model protected mode from a
-; hard-coded GDT that provides exactly two descriptors.
-; This is a bare bones transition to protected mode only
-; used for a while in PEI and possibly DXE.
-;
-; After enabling protected mode, a far jump is executed to
-; transfer to PEI using the newly loaded GDT.
-;
-; Return: None
-;
-;----------------------------------------------------------------------------
-align 16
-_ModuleEntryPoint PROC C PUBLIC
- ;
- ; Load the GDT table in GdtDesc
- ;
- mov esi, OFFSET GdtDesc
- db 66h
- lgdt fword ptr cs:[si]
+RET_ESI MACRO
- ;
- ; Transition to 16 bit protected mode
- ;
- mov eax, cr0 ; Get control register 0
- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
- mov cr0, eax ; Activate protected mode
+ movd esi, mm7 ; restore ESP from MM7
+ jmp esi
- ;
- ; Now we're in 16 bit protected mode
- ; Set up the selectors for 32 bit protected mode entry
- ;
- mov ax, SYS_DATA_SEL
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
+ENDM
- ;
- ; Transition to Flat 32 bit protected mode
- ; The jump to a far pointer causes the transition to 32 bit mode
- ;
- mov esi, offset ProtectedModeEntryLinearAddress
- jmp fword ptr cs:[si]
+;
+; Perform early platform initialization
+;
+SecPlatformInit PROC NEAR PUBLIC
-_ModuleEntryPoint ENDP
+ RET_ESI
-_TEXT_REALMODE ENDS
+SecPlatformInit ENDP
-.code
;
; Protected mode portion initializes stack, configures cache, and calls C
entry point
;
@@ -125,7 +74,6 @@ ProtectedModeEntryPoint PROC NEAR C PUBLIC
; Dummy function. Consume 2 API to make sure they can be linked.
;
mov eax, TempRamInitApi
- mov eax, FspInitApi
; Should never return
jmp $
diff --git a/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.s
b/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.s
index 4136e76..d46d792 100644
--- a/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.s
+++ b/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.s
@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD
License
# which accompanies this distribution. The full text of the license may be
found at
@@ -21,71 +21,11 @@
# Contrary to the name, this file contains 16 bit code as well.
#
.text
-#----------------------------------------------------------------------------
-#
-# Procedure: _ModuleEntryPoint
-#
-# Input: None
-#
-# Output: None
-#
-# Destroys: Assume all registers
-#
-# Description:
-#
-# Transition to non-paged flat-model protected mode from a
-# hard-coded GDT that provides exactly two descriptors.
-# This is a bare bones transition to protected mode only
-# used for a while in PEI and possibly DXE.
-#
-# After enabling protected mode, a far jump is executed to
-# transfer to PEI using the newly loaded GDT.
-#
-# Return: None
-#
-#----------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
-ASM_PFX(_ModuleEntryPoint):
- #
- # Load the GDT table in GdtDesc
- #
- .byte 0x66,0xbe #movl $GdtDesc, %esi
- .long GdtDesc
-
- .byte 0x66,0x2e,0x0f,0x01,0x14 #lgdt %cs:(%si)
-
- #
- # Transition to 16 bit protected mode
- #
- .byte 0x0f,0x20,0xc0 #movl %cr0, %eax # Get
control register 0
- .byte 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE
bit (bit #0) & MP bit (bit #1)
- .byte 0x0f,0x22,0xc0 #movl %eax, %cr0 # Activate
protected mode
-
- #
- # Now we're in 16 bit protected mode
- # Set up the selectors for 32 bit protected mode entry
- #
- .byte 0xb8 #movw SYS_DATA_SEL, %ax
- .word SYS_DATA_SEL
-
- .byte 0x8e,0xd8 #movw %ax, %ds
- .byte 0x8e,0xc0 #movw %ax, %es
- .byte 0x8e,0xe0 #movw %ax, %fs
- .byte 0x8e,0xe8 #movw %ax, %gs
- .byte 0x8e,0xd0 #movw %ax, %ss
-
- #
- # Transition to Flat 32 bit protected mode
- # The jump to a far pointer causes the transition to 32 bit mode
- #
- .byte 0x66,0xbe #movl ProtectedModeEntryLinearAddress, %esi
- .long ProtectedModeEntryLinearAddress
- .byte 0x66,0x2e,0xff,0x2c #jmp %cs:(%esi)
-
-#
-# Protected mode portion initializes stack, configures cache, and calls C
entry point
-#
+ASM_GLOBAL ASM_PFX(SecPlatformInit)
+ASM_PFX(SecPlatformInit):
+ movd %mm7, %esi # restore ESP from MM7
+ jmp *%esi
#----------------------------------------------------------------------------
#
@@ -117,7 +57,6 @@ ProtectedModeEntryPoint:
# Dummy function. Consume 2 API to make sure they can be linked.
#
movl ASM_PFX(TempRamInitApi), %eax
- movl ASM_PFX(FspInitApi), %eax
#
# Should never return
#
diff --git a/IntelFspPkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
b/IntelFspPkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
index d72d05f..7bb95a9 100644
--- a/IntelFspPkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
+++ b/IntelFspPkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
@@ -1,7 +1,7 @@
/** @file
Null instance of Platform Sec Lib.
- Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -13,6 +13,7 @@
**/
#include <PiPei.h>
+#include <Library/FspCommonLib.h>
/**
This function check the signture of UPD.
@@ -30,5 +31,3 @@ FspUpdSignatureCheck (
{
return EFI_SUCCESS;
}
-
-
--
2.7.4.windows.1
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