On 07/14/16 18:33, Paolo Bonzini wrote:
>
>
> On 14/07/2016 13:19, Laszlo Ersek wrote:
>> The problem is that NASM wouldn't support segment register MOVs in
>> 64-bit mode until the following commit:
>>
>> http://repo.or.cz/nasm.git/commitdiff/21d4ccc3c338
>>
>> Wed, 25 Aug 2010 02:28:00 +0200 (24 17:28 -0700)
>>
>> However, that change was first released in NASM 2.10:
>>
>> http://repo.or.cz/nasm.git/commitdiff/ff62f33da0a2
>>
>> Mon, 12 Mar 2012 21:36:02 +0100 (12 13:36 -0700)
>>
>> I tried to work around this; for example by using
>>
>> movzx eax, ds
>
> You can just say "mov eax, ds" (and "mov ds, eax"). The reason is that
> 32-bit destination operands are automatically zero-extended to 64-bit.
* The "zx" in the above was not about zero extending from 32 to 64 (I
read in the SDM or maybe on StackOverflow that that would happen
automatically, when writing eax and then reading rax). Instead, the
"zx" was for zero extending from 16 (ds) to 32 (eax).
* I didn't say, but I also tried "mov ax, ds". The SDM writes, "The
upper 56 bits or 48 bits (respectively) of the destination
general-purpose register are not modified by the operation". In this
context, those bits were known to be zero, and I hoped that NASM 2.07
might support a 16->16 MOV.
I vaguely recall that I tried "mov eax, ds" too (it may have been my
very first try, I don't remember any longer). I think "mov ax, ds" was
my second try, and "movzx eax, ds" the third?...
However, none of these work, because NASM 2.07 (apparently) lacks the
*general* ability to MOV from/to segment registers in 64-bit mode.
> In fact if you check the SDM only movsx supports 64-bit destinations,
> while for movzx you just use a 32-bit destination.
MOV seems to support 16-bit segment register --> 64 bit register or memory:
Opcode Instruction Op/ 64-Bit Compat/
En Mode Leg Mode
------------- ---------------- --- ------ --------
REX.W + 8C /r MOV r/m64,Sreg** A Valid Valid
Description: Move zero extended 16-bit segment register to r/m64.
** In 32-bit mode, the assembler may insert the 16-bit operand-size
prefix with this instruction (see the following “Description”
section for further information).
(I.e., I believe that the original NASM source code is correct.)
Thanks
Laszlo
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