Hi, Mike Thanks for providing such info.
I double checked WDK7600.16385.1 msahci driver. In P_Running_WaitOnFRE(), there is a statement: " Wait for confirmation is a 'nice to have' but isn't necessary. " And in the code, it waits for 50ms for FR bit if it's not set to 1. So the most safe way to follow windows & linux implementation is to add a 50ms delay whatever FR is set or not. But no spec speaks this 50ms delay. I would prefer to leave it as is and we can fix it after we get real h/w issue report. Thanks Feng -----Original Message----- From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Mike Maslenkin Sent: Friday, July 15, 2016 5:59 AM To: Tian, Feng <feng.t...@intel.com> Cc: edk2-devel@lists.01.org Subject: Re: [edk2] SATA AHCI issue BTW Windows waits for FR bit set for 50ms as opposed to Linux. See P_Running_WaitOnFRE function of storahci from WDK. So you can break Intel HBAs for example. Could you ask iastor team about this issue? Regards. On Thu, 2016-07-14 at 06:25 +0000, Tian, Feng wrote: > Hi, Shaveta > > We have approved this fix. Do you miss it? > http://article.gmane.org/gmane.comp.bios.edk2.devel/13541 > > Thanks > Feng > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of > Shaveta Leekha > Sent: Thursday, July 14, 2016 2:04 PM > To: edk2-devel@lists.01.org; Linaro UEFI Mailman List > <linaro-u...@lists.linaro.org>; Jan Dąbroś <j...@semihalf.com>; Ard > Biesheuvel <ard.biesheu...@linaro.org> > Cc: Ruchika Gupta <ruchika.gu...@nxp.com> > Subject: [edk2] SATA AHCI issue > > Hi, > > > > I have been working on support for AHCI controller for my ARMv8 platform. > > For that I have integrated my PciEmulation code and SataControllerDxe driver > code with MdeModulePkg/Bus/Ata. > > > > But facing one issue, this is same issue reported by Jan Dabros(in To list) > sometime back. > > Setting PxCMD.FRE bit of command register doesn't cause PxCMD.FR to be set to > '1' even after "500msec" timeout. > > > > (As per AHCI spec 1.3 : When PxCMD.FRE is set, it causes PxCMD.FR to be set > to '1' ) > > Is it correct to just comment out following code part from > "MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c" file, > "AhciModeInitialization" function: > > > > As Initialization timeouts is occurring in below part of code: > > > > // > > // Enable FIS Receive DMA engine for the first D2H FIS. > > // > > Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + > EFI_AHCI_PORT_CMD; > > AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE); > > Status = AhciWaitMmioSet ( > > PciIo, > > Offset, > > EFI_AHCI_PORT_CMD_FR, > > EFI_AHCI_PORT_CMD_FR, > > EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT > > ); > > if (EFI_ERROR (Status)) { > > continue; > > } > > > > And if above code is commented out, then SATA stack works completely fine. > > > > What can be the problem? > > > > Thank you in advance for your time! > > > > Best regards, > > Shaveta > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
