https://bugzilla.tianocore.org/show_bug.cgi?id=201
Cc: Giri P Mudusuru <giri.p.mudus...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming....@intel.com> --- MdePkg/Include/IndustryStandard/SdramSpd.h | 1682 +++++++++++++++++++++++++++- 1 file changed, 1670 insertions(+), 12 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/SdramSpd.h b/MdePkg/Include/IndustryStandard/SdramSpd.h index 2b2012b..e3f6eea 100644 --- a/MdePkg/Include/IndustryStandard/SdramSpd.h +++ b/MdePkg/Include/IndustryStandard/SdramSpd.h @@ -1,14 +1,24 @@ /** @file This file contains definitions for the SPD fields on an SDRAM. - - Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @par Revision Reference: + - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6 + http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf + + - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4 + http://www.jedec.org/standards-documents/docs/spd412l-4 + + - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2 + http://www.jedec.org/standards-documents/docs/spd412m-2 **/ #ifndef _SDRAM_SPD_H_ @@ -47,9 +57,14 @@ // // Memory Type Definitions // -#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory -#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory -#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory +#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory +#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory +#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory +#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory +#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory +#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory +#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory + // // ECC Type Definitions // @@ -62,4 +77,1647 @@ #define SPD_BUFFERED 0x01 #define SPD_REGISTERED 0x02 +#pragma pack (push, 1) + +typedef union { + struct { + UINT8 BytesUsed : 4; ///< Bits 3:0 + UINT8 BytesTotal : 3; ///< Bits 6:4 + UINT8 CrcCoverage : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_DEVICE_DESCRIPTION_STRUCT; + +typedef union { + struct { + UINT8 Minor : 4; ///< Bits 3:0 + UINT8 Major : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_REVISION_STRUCT; + +typedef union { + struct { + UINT8 Type : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_DRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 3; ///< Bits 6:4 + UINT8 Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 ColumnAddress : 3; ///< Bits 2:0 + UINT8 RowAddress : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_SDRAM_ADDRESSING_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_50 : 1; ///< Bits 0:0 + UINT8 OperationAt1_35 : 1; ///< Bits 1:1 + UINT8 OperationAt1_25 : 1; ///< Bits 2:2 + UINT8 Reserved : 5; ///< Bits 7:3 + } Bits; + UINT8 Data; +} SPD_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 + UINT8 RankCount : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 + UINT8 BusWidthExtension : 2; ///< Bits 4:3 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + UINT8 Divisor : 4; ///< Bits 3:0 + UINT8 Dividend : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_FINE_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT8 Dividend : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT; + +typedef union { + struct { + UINT8 Divisor : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT; + +typedef struct { + SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend + SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor +} SPD_MEDIUM_TIMEBASE; + +typedef union { + struct { + UINT8 tCKmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TCK_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 CL4 : 1; ///< Bits 0:0 + UINT16 CL5 : 1; ///< Bits 1:1 + UINT16 CL6 : 1; ///< Bits 2:2 + UINT16 CL7 : 1; ///< Bits 3:3 + UINT16 CL8 : 1; ///< Bits 4:4 + UINT16 CL9 : 1; ///< Bits 5:5 + UINT16 CL10 : 1; ///< Bits 6:6 + UINT16 CL11 : 1; ///< Bits 7:7 + UINT16 CL12 : 1; ///< Bits 8:8 + UINT16 CL13 : 1; ///< Bits 9:9 + UINT16 CL14 : 1; ///< Bits 10:10 + UINT16 CL15 : 1; ///< Bits 11:11 + UINT16 CL16 : 1; ///< Bits 12:12 + UINT16 CL17 : 1; ///< Bits 13:13 + UINT16 CL18 : 1; ///< Bits 14:14 + UINT16 Reserved : 1; ///< Bits 15:15 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 tAAmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TAA_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TWR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRRDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRRD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tCCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TCCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TWR_UPPER_NIBBLE_STRUCT; + +typedef union { + struct { + UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0 + UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TWTR_UPPER_NIBBLE_STRUCT; + +typedef union { + struct { + UINT8 tRPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPab : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRP_AB_MTB_STRUCT; + +typedef union { + struct { + INT8 tRPabFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRP_AB_FTB_STRUCT; + +typedef union { + struct { + UINT8 tRPpb : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRP_PB_MTB_STRUCT; + +typedef union { + struct { + INT8 tRPpbFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRP_PB_FTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCab : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TRFC_AB_MTB_STRUCT; + +typedef union { +struct { + UINT16 tRFCpb : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TRFC_PB_MTB_STRUCT; + +typedef union { + struct { + UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0 + UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5 + UINT8 PackageRankMap : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_CONNECTOR_BIT_MAPPING_BYTE_STRUCT; + +typedef union { + struct { + UINT8 tRASminUpper : 4; ///< Bits 3:0 + UINT8 tRCminUpper : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TRAS_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRAS_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCmin : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TRFC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWTRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TWTR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRTPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRTP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tFAWminUpper : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TFAW_MIN_MTB_UPPER_STRUCT; + +typedef union { + struct { + UINT8 tFAWmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TFAW_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 RZQ6 : 1; ///< Bits 0:0 + UINT8 RZQ7 : 1; ///< Bits 1:1 + UINT8 Reserved : 5; ///< Bits 6:2 + UINT8 DllOff : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0 + UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1 + UINT8 AutoSelfRefresh : 1; ///< Bits 2:2 + UINT8 OnDieThermalSensor : 1; ///< Bits 3:3 + UINT8 Reserved : 3; ///< Bits 6:4 + UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 Reserved : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramDeviceType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + INT8 tCKminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TCK_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tAAminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TAA_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRPminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRP_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRC_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT8 MaximumActivateCount : 4; ///< Bits 3:0 + UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 + UINT8 VendorSpecific : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_MAXIMUM_ACTIVE_COUNT_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 HybridMedia : 3; ///< Bits 6:4 + UINT8 Hybrid : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 2; ///< Bits 5:4 + UINT8 BankGroup : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 5; ///< Bits 4:0 + UINT8 SoftPPR : 1; ///< Bits 5:5 + UINT8 PostPackageRepair : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 DRAMDensityRatio : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramDeviceType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 + UINT8 RankCount : 3; ///< Bits 5:3 + UINT8 RankMix : 1; ///< Bits 6:6 + UINT8 Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_20 : 1; ///< Bits 0:0 + UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 + UINT8 Reserved : 6; ///< Bits 7:2 + } Bits; + UINT8 Data; +} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 tCKmax : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TCK_MAX_MTB_STRUCT; + +typedef union { + struct { + INT8 tCKmaxFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TCK_MAX_FTB_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 Fine : 2; ///< Bits 1:0 + UINT8 Medium : 2; ///< Bits 3:2 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT32 CL7 : 1; ///< Bits 0:0 + UINT32 CL8 : 1; ///< Bits 1:1 + UINT32 CL9 : 1; ///< Bits 2:2 + UINT32 CL10 : 1; ///< Bits 3:3 + UINT32 CL11 : 1; ///< Bits 4:4 + UINT32 CL12 : 1; ///< Bits 5:5 + UINT32 CL13 : 1; ///< Bits 6:6 + UINT32 CL14 : 1; ///< Bits 7:7 + UINT32 CL15 : 1; ///< Bits 8:8 + UINT32 CL16 : 1; ///< Bits 9:9 + UINT32 CL17 : 1; ///< Bits 10:10 + UINT32 CL18 : 1; ///< Bits 11:11 + UINT32 CL19 : 1; ///< Bits 12:12 + UINT32 CL20 : 1; ///< Bits 13:13 + UINT32 CL21 : 1; ///< Bits 14:14 + UINT32 CL22 : 1; ///< Bits 15:15 + UINT32 CL23 : 1; ///< Bits 16:16 + UINT32 CL24 : 1; ///< Bits 17:17 + UINT32 CL25 : 1; ///< Bits 18:18 + UINT32 CL26 : 1; ///< Bits 19:19 + UINT32 CL27 : 1; ///< Bits 20:20 + UINT32 CL28 : 1; ///< Bits 21:21 + UINT32 CL29 : 1; ///< Bits 22:22 + UINT32 CL30 : 1; ///< Bits 23:23 + UINT32 CL31 : 1; ///< Bits 24:24 + UINT32 CL32 : 1; ///< Bits 25:25 + UINT32 CL33 : 1; ///< Bits 26:26 + UINT32 CL34 : 1; ///< Bits 27:27 + UINT32 CL35 : 1; ///< Bits 28:28 + UINT32 CL36 : 1; ///< Bits 29:29 + UINT32 Reserved : 1; ///< Bits 30:30 + UINT32 CLrange : 1; ///< Bits 31:31 + } Bits; + struct { + UINT32 CL23 : 1; ///< Bits 0:0 + UINT32 CL24 : 1; ///< Bits 1:1 + UINT32 CL25 : 1; ///< Bits 2:2 + UINT32 CL26 : 1; ///< Bits 3:3 + UINT32 CL27 : 1; ///< Bits 4:4 + UINT32 CL28 : 1; ///< Bits 5:5 + UINT32 CL29 : 1; ///< Bits 6:6 + UINT32 CL30 : 1; ///< Bits 7:7 + UINT32 CL31 : 1; ///< Bits 8:8 + UINT32 CL32 : 1; ///< Bits 9:9 + UINT32 CL33 : 1; ///< Bits 10:10 + UINT32 CL34 : 1; ///< Bits 11:11 + UINT32 CL35 : 1; ///< Bits 12:12 + UINT32 CL36 : 1; ///< Bits 13:13 + UINT32 CL37 : 1; ///< Bits 14:14 + UINT32 CL38 : 1; ///< Bits 15:15 + UINT32 CL39 : 1; ///< Bits 16:16 + UINT32 CL40 : 1; ///< Bits 17:17 + UINT32 CL41 : 1; ///< Bits 18:18 + UINT32 CL42 : 1; ///< Bits 19:19 + UINT32 CL43 : 1; ///< Bits 20:20 + UINT32 CL44 : 1; ///< Bits 21:21 + UINT32 CL45 : 1; ///< Bits 22:22 + UINT32 CL46 : 1; ///< Bits 23:23 + UINT32 CL47 : 1; ///< Bits 24:24 + UINT32 CL48 : 1; ///< Bits 25:25 + UINT32 CL49 : 1; ///< Bits 26:26 + UINT32 CL50 : 1; ///< Bits 27:27 + UINT32 CL51 : 1; ///< Bits 28:28 + UINT32 CL52 : 1; ///< Bits 29:29 + UINT32 Reserved : 1; ///< Bits 30:30 + UINT32 CLrange : 1; ///< Bits 31:31 + } HighRangeBits; + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_EXTENDED_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ChipSelectLoading : 3; ///< Bits 2:0 + UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3 + UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_SIGNAL_LOADING_STRUCT; + +typedef union { + struct { + UINT8 MaximumActivateCount : 4; ///< Bits 3:0 + UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + INT8 tCCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TCCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRRDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRRD_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 HybridMedia : 3; ///< Bits 6:4 + UINT8 Hybrid : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 2; ///< Bits 5:4 + UINT8 BankGroup : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 + UINT8 BusWidthExtension : 2; ///< Bits 4:3 + UINT8 NumberofChannels : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT32 CL3 : 1; ///< Bits 0:0 + UINT32 CL6 : 1; ///< Bits 1:1 + UINT32 CL8 : 1; ///< Bits 2:2 + UINT32 CL9 : 1; ///< Bits 3:3 + UINT32 CL10 : 1; ///< Bits 4:4 + UINT32 CL11 : 1; ///< Bits 5:5 + UINT32 CL12 : 1; ///< Bits 6:6 + UINT32 CL14 : 1; ///< Bits 7:7 + UINT32 CL16 : 1; ///< Bits 8:8 + UINT32 Reserved0 : 1; ///< Bits 9:9 + UINT32 CL20 : 1; ///< Bits 10:10 + UINT32 CL22 : 1; ///< Bits 11:11 + UINT32 CL24 : 1; ///< Bits 12:12 + UINT32 Reserved1 : 1; ///< Bits 13:13 + UINT32 CL28 : 1; ///< Bits 14:14 + UINT32 Reserved2 : 1; ///< Bits 15:15 + UINT32 CL32 : 1; ///< Bits 16:16 + UINT32 Reserved3 : 1; ///< Bits 17:17 + UINT32 CL36 : 1; ///< Bits 18:18 + UINT32 Reserved4 : 1; ///< Bits 19:19 + UINT32 CL40 : 1; ///< Bits 20:20 + UINT32 Reserved5 : 11; ///< Bits 31:21 + } Bits; + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 ChannelsPerDie : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramPackageType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_20 : 1; ///< Bits 0:0 + UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 + UINT8 OperationAt1_10 : 1; ///< Bits 2:2 + UINT8 EndurantAt1_10 : 1; ///< Bits 3:3 + UINT8 OperationAtTBD2V : 1; ///< Bits 4:4 + UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 ReadLatencyMode : 2; ///< Bits 1:0 + UINT8 WriteLatencySet : 2; ///< Bits 3:2 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 MaximumActivateCount : 4; ///< Bits 3:0 + UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 5; ///< Bits 4:0 + UINT8 SoftPPR : 1; ///< Bits 5:5 + UINT8 PostPackageRepair : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_UNBUF_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_UNBUF_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 MappingRank1 : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD_UNBUF_ADDRESS_MAPPING; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_RDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_RDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 RegisterType : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_RDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 + UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_MANUFACTURER_ID_CODE; + +typedef union { + struct { + UINT8 RegisterRevisionNumber; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_RDIMM_REGISTER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 Bit0 : 1; ///< Bits 0:0 + UINT8 Bit1 : 1; ///< Bits 1:1 + UINT8 Bit2 : 1; ///< Bits 2:2 + UINT8 Reserved : 5; ///< Bits 7:3 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_TYPE; + +typedef union { + struct { + UINT8 Reserved : 4; ///< Bits 0:3 + UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4 + UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS; + +typedef union { + struct { + UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1 + UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2 + UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4 + UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK; + +typedef union { + struct { + UINT8 Reserved0 : 4; ///< Bits 0:3 + UINT8 Reserved1 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_CONTROL_RESERVED; + +typedef union { + struct { + UINT8 Rank1Mapping : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM; + +typedef union { + struct { + UINT8 CKE : 2; ///< Bits 1:0 + UINT8 ODT : 2; ///< Bits 3:2 + UINT8 CommandAddress : 2; ///< Bits 5:4 + UINT8 ChipSelect : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS; + +typedef union { + struct { + UINT8 Y0Y2 : 2; ///< Bits 1:0 + UINT8 Y1Y3 : 2; ///< Bits 3:2 + UINT8 Reserved0 : 2; ///< Bits 5:4 + UINT8 RCDOutputSlewRateControl : 1; ///< Bits 6:6 + UINT8 Reserved1 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LRDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LRDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LRDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 RegisterType : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LRDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT8 MinimumDelayTime : 7; ///< Bits 0:6 + UINT8 Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MODULE_DELAY_TIME; + +typedef union { + struct { + UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0 + UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1 + UINT8 Reserved0 : 1; ///< Bits 2:2 + UINT8 Reserved1 : 1; ///< Bits 3:3 + UINT8 AddressCommandOutputs : 2; ///< Bits 5:4 + UINT8 QxCS_nOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 QxODTOutputs : 2; ///< Bits 1:0 + UINT8 QxCKEOutputs : 2; ///< Bits 3:2 + UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4 + UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 YExtendedDelay : 2; ///< Bits 1:0 + UINT8 QxCS_n : 2; ///< Bits 3:2 + UINT8 QxODT : 2; ///< Bits 5:4 + UINT8 QxCKE : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_EXTENDED_DELAY; + +typedef union { + struct { + UINT8 DelayY : 3; ///< Bits 2:0 + UINT8 Reserved : 1; ///< Bits 3:3 + UINT8 QxCS_n : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA; + +typedef union { + struct { + UINT8 QxCS_n : 4; ///< Bits 3:0 + UINT8 QxODT : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE; + +typedef union { + struct { + UINT8 RC8MDQODTStrength : 3; ///< Bits 2:0 + UINT8 RC8Reserved : 1; ///< Bits 3:3 + UINT8 RC9MDQODTStrength : 3; ///< Bits 6:4 + UINT8 RC9Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0 + UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1 + UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2 + UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3 + UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4 + UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5 + UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6 + UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL; + +typedef union { + struct { + UINT8 Driver_Impedance : 2; ///< Bits 1:0 + UINT8 Rtt_Nom : 3; ///< Bits 4:2 + UINT8 Reserved : 1; ///< Bits 5:5 + UINT8 Rtt_WR : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MR_1_2; + +typedef union { + struct { + UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 + UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION; + +typedef union { + struct { + UINT8 RegisterRevisionNumber; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REGISTER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 Rank1Mapping : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM; + +typedef union { + struct { + UINT8 CKE : 2; ///< Bits 1:0 + UINT8 ODT : 2; ///< Bits 3:2 + UINT8 CommandAddress : 2; ///< Bits 5:4 + UINT8 ChipSelect : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS; + +typedef union { + struct { + UINT8 Y0Y2 : 2; ///< Bits 1:0 + UINT8 Y1Y3 : 2; ///< Bits 3:2 + UINT8 Reserved0 : 2; ///< Bits 5:4 + UINT8 RCDOutputSlewRateControl : 1; ///< Bits 6:6 + UINT8 Reserved1 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK; + +typedef struct { + UINT8 DataBufferRevisionNumber; +} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 DRAMVrefDQforPackageRank0 : 6; ///< Bits 5:0 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK; + +typedef struct { + UINT8 DataBufferVrefDQforDRAMInterface; +} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE; + +typedef union { + struct { + UINT8 DRAMInterfaceMDQDriveStrength : 4; ///< Bits 3:0 + UINT8 DRAMInterfaceMDQReadTerminationStrength : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE; + +typedef union { + struct { + UINT8 DatarateLe1866 : 2; ///< Bits 1:0 + UINT8 DatarateLe2400 : 2; ///< Bits 3:2 + UINT8 DatarateLe3200 : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 RTT_NOM : 3; ///< Bits 2:0 + UINT8 RTT_WR : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE; + +typedef union { + struct { + UINT8 PackageRanks0_1 : 3; ///< Bits 2:0 + UINT8 PackageRanks2_3 : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE; + +typedef union { + struct { + UINT8 Rank0 : 1; ///< Bits 0:0 + UINT8 Rank1 : 1; ///< Bits 1:1 + UINT8 Rank2 : 1; ///< Bits 2:2 + UINT8 Rank3 : 1; ///< Bits 3:3 + UINT8 DataBuffer : 1; ///< Bits 4:4 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE; + +typedef union { + struct { + UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0 + UINT8 DataBufferDFE : 1; ///< Bits 1:1 + UINT8 Reserved : 6; ///< Bits 7:2 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION; + +typedef struct { + UINT8 LSB; + UINT8 MSB; +} SPD_NVDIMM_MODULE_PRODUCT_IDENTIFIER; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE; + +typedef struct { + UINT8 LSB; + UINT8 MSB; +} SPD_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER; + +typedef UINT8 SPD_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_NVDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 Reserved : 4; ///< Bits 3:0 + UINT8 Extension : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_NVDIMM_MODULE_CHARACTERISTICS; + +typedef struct { + UINT8 Reserved; + UINT8 MediaType; +} SPD_NVDIMM_HYBRID_MODULE_MEDIA_TYPES; + +typedef UINT8 SPD_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME; + +typedef union { + struct { + UINT16 FunctionInterface : 5; ///< Bits 4:0 + UINT16 FunctionClass : 5; ///< Bits 9:5 + UINT16 BlockOffset : 4; ///< Bits 13:10 + UINT16 Reserved : 1; ///< Bits 14:14 + UINT16 Implemented : 1; ///< Bits 15:15 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR; + +typedef struct { + UINT8 Year; ///< Year represented in BCD (00h = 2000) + UINT8 Week; ///< Year represented in BCD (47h = week 47) +} SPD_MANUFACTURING_DATE; + +typedef union { + UINT32 Data; + UINT16 SerialNumber16[2]; + UINT8 SerialNumber8[4]; +} SPD_MANUFACTURER_SERIAL_NUMBER; + +typedef struct { + UINT8 Location; ///< Module Manufacturing Location +} SPD_MANUFACTURING_LOCATION; + +typedef struct { + SPD_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code + SPD_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location + SPD_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) + SPD_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number +} SPD_UNIQUE_MODULE_ID; + +typedef union { + UINT16 Crc[1]; + UINT8 Data8[2]; +} SPD_CYCLIC_REDUNDANCY_CODE; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD + SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width + SPD_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor + SPD_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin) + UINT8 Reserved0; ///< 13 Reserved + SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin) + SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin) + SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) + SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin) + SPD_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features + SPD_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options + SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor + SPD_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin) + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved + SPD_MAXIMUM_ACTIVE_COUNT_STRUCT MACValue; ///< 41 SDRAM Maximum Active Count (MAC) Value + UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved +} SPD3_BASE_SECTION; + +typedef struct { + SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM + UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved +} SPD3_MODULE_UNBUFFERED; + +typedef struct { + SPD_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes + SPD_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution + SPD_MANUFACTURER_ID_CODE RegisterManufacturerIDCode; ///< 65-66 Register Manufacturer ID Code + SPD_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number + SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address + SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved + UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved +} SPD3_MODULE_REGISTERED; + +typedef struct { + SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved +} SPD3_MODULE_CLOCKED; + +typedef struct { + SPD_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes + UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number + SPD_MANUFACTURER_ID_CODE ManufacturerIDCode; ///< 65-66 Memory Buffer Manufacturer ID Code + SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCACS; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS + SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y + SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE + SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCSCA; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA + SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForODTCKE; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MDQTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxODTControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxODTControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxODTControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxODTControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066 + SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MDQTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxODTControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxODTControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxODTControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxODTControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066 + SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MDQTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxODTControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxODTControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxODTControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxODTControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066 + SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V + SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V + SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V + SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V + SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V + SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V + UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved + UINT8 PersonalityByte[116 - 102 + 1]; ///< 116-102 Memory Buffer Personality Bytes +} SPD3_MODULE_LOADREDUCED; + +typedef union { + SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types + SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types + SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types + SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types +} SPD3_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number +} SPD3_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code +} SPD3_MODULE_REVISION_CODE; + +typedef struct { + UINT8 ManufactureSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data +} SPD3_MANUFACTURE_SPECIFIC; + +/// +/// DDR3 Serial Presence Detect structure +/// +typedef struct { + SPD3_BASE_SECTION General; ///< 0-59 General Section + SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section + SPD_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) + SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number + SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code + SPD3_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 150-175 Manufacturer's Specific Data + UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use +} SPD_DDR3; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 6 Primary SDRAM Package Type + SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features + SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options + SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features + SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramDeviceType;///< 10 Secondary SDRAM Package Type + SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD + SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width + SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor + SPD_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type + UINT8 Reserved0; ///< 16 Reserved + SPD_TIMEBASE_STRUCT Timebase; ///< 17 Timebases + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) + SPD_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) + SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min) + SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min) + SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin) + SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group + SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group + SPD_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group + SPD_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin + SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin) + SPD_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin + SPD_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group + SPD_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group + UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved + SPD_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1];///< 60-77 Connector to SDRAM Bit Mapping + UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved + SPD_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group + SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group + SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax) + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin) + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) +} SPD4_BASE_SECTION; + +typedef struct { + SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM + UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_UNBUFFERED; + +typedef struct { + SPD_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes + SPD_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution + SPD_MANUFACTURER_ID_CODE RegisterManufacturerIDCode; ///< 133-134 Register Manufacturer ID Code + SPD_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number + SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM + SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlAndCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address + SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock + UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_REGISTERED; + +typedef struct { + SPD_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + SPD_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes + SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution + SPD_MANUFACTURER_ID_CODE RegisterManufacturerIDCode; ///< 133-134 Register Manufacturer ID Code + SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number + SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM + SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlAndCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address + SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock + SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DRAMVrefDQforPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0 + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DRAMVrefDQforPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1 + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DRAMVrefDQforPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2 + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DRAMVrefDQforPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3 + SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQforDRAMInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface + SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMDQDriveStrengthandRTTfordatarateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866 + SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMDQDriveStrengthandRTTfordatarateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400 + SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMDQDriveStrengthandRTTfordatarateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200 + SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DRAMDriveStrength; ///< 148 DRAM Drive Strength + SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DRAMODTRTT_WRandRTT_NOMfordatarateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866 + SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DRAMODTRTT_WRandRTT_NOMfordatarateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400 + SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DRAMODTRTT_WRandRTT_NOMfordatarateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200 + SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DRAMODTRTT_PARKfordatarateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866 + SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DRAMODTRTT_PARKfordatarateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400 + SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DRAMODTRTT_PARKfordatarateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200 + SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQforDRAMInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range + SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDQDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization + UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_LOADREDUCED; + +typedef struct { + UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 + SPD_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier + SPD_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIDCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code + SPD_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier + SPD_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code + SPD_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used + SPD_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics + SPD_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types + SPD_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time + SPD_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors + UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_NVDIMM; + +typedef union { + SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types + SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types + SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types + SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters +} SPD4_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number +} SPD4_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ManufactureSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data +} SPD4_MANUFACTURE_SPECIFIC; + +typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code +typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping + +typedef struct { + SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID + SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number + SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code + SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping + SPD4_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-381 Manufacturer's Specific Data + UINT8 Reserved[2]; ///< 382-383 Reserved +} SPD4_MANUFACTURING_DATA; + +typedef struct { + UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types +} SPD4_END_USER_SECTION; + +/// +/// DDR4 Serial Presence Detect structure +/// +typedef struct { + SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters + SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section + UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved + SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information + SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable +} SPD_DDR4; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type + SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features + SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options + SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures;///< 9 Other SDRAM Optional Features + UINT8 Reserved0; ///< 10 Reserved + SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD + SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization + SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width + SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor + SPD_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type + SPD_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading + SPD_TIMEBASE_STRUCT Timebase; ///< 17 Timebases + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) + SPD_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) + SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) + SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks + SPD_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank + SPD_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks + SPD_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank + UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved + SPD_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping + UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved + SPD_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank + SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax) + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) +} SPD_LPDDR_BASE_SECTION; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_REFERENCE_RAW_CARD; + +typedef struct { + SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD_LPDDR_MODULE_LPDIMM; + +typedef struct { + SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types +} SPD_LPDDR_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number +} SPD_LPDDR_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ManufactureSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data +} SPD_LPDDR_MANUFACTURE_SPECIFIC; + +typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code +typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping + +typedef struct { + SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID + SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number + SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code + SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping + SPD_LPDDR_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-381 Manufacturer's Specific Data + UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved +} SPD_LPDDR_MANUFACTURING_DATA; + +typedef struct { + UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable +} SPD_LPDDR_END_USER_SECTION; + +/// +/// LPDDR Serial Presence Detect structure +/// +typedef struct { + SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters + SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section + UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters + SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information + SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable +} SPD_LPDDR; + +#pragma pack (pop) #endif -- 2.8.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
