Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex. This library is derived from Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford <stelf...@cadence.com> --- .../Library/CadencePciHostBridgeLib/CdnsPci.c | 103 +++++++++++ .../Library/CadencePciHostBridgeLib/CdnsPci.h | 85 +++++++++ .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 189 +++++++++++++++++++++ .../CdnsPciHostBridgeLib.inf | 77 +++++++++ 4 files changed, 454 insertions(+) create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c new file mode 100644 index 0000000..afab354 --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c @@ -0,0 +1,103 @@ +/** @file +* Initialize the Cadence PCIe Root complex +* +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/BaseLib.h> +#include <Library/CspSysReg.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/Cpu.h> + +#include "CdnsPci.h" + +STATIC +VOID +CdnsPciRegInit( + EFI_CPU_IO2_PROTOCOL *CpuIo +) +{ + UINT32 Value; + + // Setup the class code as PCIe Host Bridge. + PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCODE); + + // Set up the BARs via the Root Port registers + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value); + PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << PCIE_RCBARPIE)); + + // Allow incoming writes + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, 0x1f); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, 0x1f); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, 0x1f); + + // Set up an area for Type 0 write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_ADDR0, 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_DESC0, PCIE_AXI_TYPE0); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_AXI_ADDR0, 0x14); + + // Set up an area for Type 1 write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_ADDR0, PCI_ECAM_BASE + (2*PCI_BUS_SIZE) + 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_DESC0, PCIE_AXI_TYPE1); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_AXI_ADDR0, (2*PCI_BUS_SIZE) + 0x18); + + // Set up an area for memory write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_ADDR0, PCI_MEM32_BASE + 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_DESC0, PCIE_AXI_MEM); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_AXI_ADDR0, PCI_ECAM_SIZE + 0x17); + + // Set up an area for IO write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_ADDR0, PCI_IO_BASE + 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_DESC0, PCIE_AXI_IO); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_AXI_ADDR0, (PCI_ECAM_SIZE + PCI_MEM32_SIZE) + 0x17 ); +} + +EFI_STATUS +HWPciRbInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 Count; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_STATUS Status; + UINT32 Value; + + PCI_TRACE ("HWPciRbInit()"); + + PCI_TRACE ("PCIe Setting up Address Translation"); + + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, + (VOID **)&CpuIo); + ASSERT_EFI_ERROR (Status); + + // Check for link up + for (Count = 0; Count < PCI_LINK_TIMEOUT_COUNT; Count++) { + gBS->Stall (PCI_LINK_TIMEOUT_WAIT_US); + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value); + if (Value & PCIE_LINK_UP) { + break; + } + } + if (!(Value & PCIE_LINK_UP)) { + DEBUG ((DEBUG_ERROR, "PCIe link not up: %x.\n", Value)); + return EFI_NOT_READY; + } + + // Initialise configuration registers + CdnsPciRegInit(CpuIo); + + return EFI_SUCCESS; +} diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h new file mode 100644 index 0000000..7d47ed6 --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h @@ -0,0 +1,85 @@ +/** @file +* Header for Cadence PCIe Root Complex +* +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __CDNS_PCI_H__ +#define __CDNS_PCI_H__ + +#include <Protocol/CpuIo2.h> + +#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress) +#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) +#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoBase) +#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) +#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) +#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) +#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) +#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) + +#define PCI_BUS_SIZE 0x00100000 + +#define PCI_LINK_TIMEOUT_WAIT_US 1000 // microseconds +#define PCI_LINK_TIMEOUT_COUNT 1000 + +#define PCI_TRACE(txt) DEBUG((DEBUG_VERBOSE, "CDNS_PCI: " txt "\n")) + +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } +#ifdef CDNS_B2B +#define PCIE1_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Value); } +#define PCIE1_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Val); } +#endif + +/* + * Bridge Internal Registers + */ + +// Root Port Configuration +#define PCIE_RP 0x00200000 +#define PCIE_PCI_CLASSCODE 0x8 + +// Local Management +#define PCIE_LM 0x00100000 +#define PCIE_LINK_CTRL_STATUS 0x00 +#define PCIE_RP_BAR_CONFIG 0x300 + +// AXI Configuration +#define PCIE_AXI 0x00400000 +#define PCIE_AXI_REG0_ADDR0 0x000 +#define PCIE_AXI_REG0_DESC0 0x008 +#define PCIE_AXI_REG0_AXI_ADDR0 0x018 +#define PCIE_AXI_REG1_ADDR0 0x020 +#define PCIE_AXI_REG1_DESC0 0x028 +#define PCIE_AXI_REG1_AXI_ADDR0 0x038 +#define PCIE_AXI_REG2_ADDR0 0x040 +#define PCIE_AXI_REG2_DESC0 0x048 +#define PCIE_AXI_REG2_AXI_ADDR0 0x058 +#define PCIE_AXI_REG3_ADDR0 0x060 +#define PCIE_AXI_REG3_DESC0 0x068 +#define PCIE_AXI_REG3_AXI_ADDR0 0x078 +#define PCIE_AXI_BAR0_IB 0x800 +#define PCIE_AXI_BAR1_IB 0x808 +#define PCIE_AXI_NO_BAR_IB 0x810 + +// Register values +#define PCIE_BRIDGE_CLASSCODE 0x06040000 +#define PCIE_LINK_UP 0x01 +#define PCIE_RCBARPIE 0x19 +#define PCIE_AXI_TYPE0 0x80000A +#define PCIE_AXI_TYPE1 0x80000B +#define PCIE_AXI_MEM 0x800002 +#define PCIE_AXI_IO 0x800006 + +#endif diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c new file mode 100644 index 0000000..7e37948 --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c @@ -0,0 +1,189 @@ +/** @file + PCI Host Bridge support for the Cadence PCIe Root Complex + + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> + Copyright (c) 2017, Cadence Design Systems. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/PciHostBridgeLib.h> + +#include <PiDxe.h> + +#include <Protocol/PciHostBridgeResourceAllocation.h> +#include <Protocol/PciRootBridgeIo.h> + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A03), // PCI + 0 + }, { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +STATIC PCI_ROOT_BRIDGE mRootBridge = { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count = 1; + + return &mRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +#ifndef MDEPKG_NDEBUG +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { + L"Mem", L"I/O", L"Bus" +}; +#endif + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf new file mode 100644 index 0000000..612fd0e --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf @@ -0,0 +1,77 @@ +## @file +# PCI Host Bridge Library instance for Cadence PCIe Root Complex +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> +# Copyright (c) 2017, Cadence Design Systems. All rights reserved. +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 1.25 + BASE_NAME = CdnsPciHostBridgeLib + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + CONSTRUCTOR = HWPciRbInit + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 ARM +# + +[Sources] + CdnsPciHostBridgeLib.c + CdnsPci.c + +[Packages] + ArmPkg/ArmPkg.dec + CadencePkg/CadenceCspPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[FixedPcd] + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciIoTranslation + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciMmio64Translation + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress + gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid -- 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
