From: Ard Biesheuvel <ard.biesheu...@linaro.org> The GIC architecture mandates that the CPU interface, which consists of 2 consecutive 4 KB frames, can be mapped using separate mappings. Since this is problematic on 64 KB pages, the MMU-400 aliases each frame 16 times, and the two consecutive frames can be found at offset 0xf000. This patch is intended to expose correct GICC alias via MADT, once ACPI support is added.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Signed-off-by: Marcin Wojtas <m...@semihalf.com> --- Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index 5071bd5..bd2336f 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -263,7 +263,14 @@ # ARM Generic Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 + + # + # NOTE: the GIC architecture mandates that the CPU interface, which consists + # of 2 consecutive 4 KB frames, can be mapped using separate mappings. + # Since this is problematic on 64 KB pages, the MMU-400 aliases each frame + # 16 times, and the two consecutive frames can be found at offset 0xf000 + # + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000 # ARM Architectural Timer Support gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
