1. Change SPI mode and speed for SueCreek
2. Update SueCreek HOST_IRQ and HOST_RST GPIO configuration
3. Add a PCD to make sure that SueCreek only reported to OS when it is actually
present on the board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yeon Sil Yoon <yeon.sil.y...@intel.com>
Signed-off-by: Guo Mang <mang....@intel.com>
---
.../Board/BensonGlacier/BoardInitPostMem/BoardGpios.h | 4 ++--
.../Board/BensonGlacier/BoardInitPostMem/BoardInit.c | 5 +++++
.../BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf | 1 +
.../Board/LeafHill/BoardInitPostMem/BoardInit.c | 5 +++++
.../Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf | 1 +
.../Board/MinnowBoard3/BoardInitPostMem/BoardInit.c | 5 +++++
.../Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf | 1 +
.../Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c | 2 ++
.../Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf | 1 +
.../Common/Acpi/AcpiTablesPCAT/GloblNvs.asl | 8 +++++++-
.../Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl | 12 +++++++-----
Platform/BroxtonPlatformPkg/PlatformPkg.dec | 2 ++
.../NorthCluster/Include/Protocol/GlobalNvsArea.h | 3 ++-
13 files changed, 41 insertions(+), 9 deletions(-)
diff --git
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
index e0bdde8..d72cd80 100644
---
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
+++
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
@@ -80,13 +80,13 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_N[] =
BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA,
GPIO_PADBAR+0x0070, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA,
GPIO_PADBAR+0x0078, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA , NA
, Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,DisPuPd,
GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in Sch:
SIM_CON_CD1, falling edge trigger
- BXT_GPIO_PAD_CONF(L"GPIO_17", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
GPIO_PADBAR+0x0088, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA
, Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd,
GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
GPIO_PADBAR+0x0090, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
GPIO_PADBAR+0x0098, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
GPIO_PADBAR+0x00A0, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA , NA
, NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
GPIO_PADBAR+0x00A8, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D , NA
, NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
GPIO_PADBAR+0x00B0, NORTH),//Feature: LB
- BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPIO ,GPIO_D , NA
, NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
GPIO_PADBAR+0x00B8, NORTH),//Feature: LB USB Power in LFH
+ BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO
, NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu,
GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D , NA
, NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0
BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D , NA
, Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , NA,
GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in Sch:
SATA_ODD_DA_IN
BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D , NA
, NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN
diff --git
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
index 8b21b50..536c390 100644
---
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
+++
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInit.c
@@ -88,6 +88,11 @@ BensonGlacierPostMemInitCallback (
//
BufferSize = sizeof (EFI_GUID);
PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8
*)&gPeiBensonGlacierVbtGuid);
+
+ //
+ // Set PcdSueCreek
+ //
+ PcdSetBool (PcdSueCreek, TRUE);
//
// Add init steps here
diff --git
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
index c22bfad..5989d30 100644
---
a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
+++
b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf
@@ -63,6 +63,7 @@
gPlatformModuleTokenSpaceGuid.PcdFabId
gPlatformModuleTokenSpaceGuid.PcdResetType
gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek
[Guids]
gEfiPlatformInfoGuid
diff --git
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
index 60fe1a3..af53b8c 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
@@ -96,6 +96,11 @@ LeafHillPostMemInitCallback (
//
BufferSize = sizeof (EFI_GUID);
PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiLeafHillVbtGuid);
+
+ //
+ // Set PcdSueCreek
+ //
+ PcdSetBool (PcdSueCreek, FALSE);
//
// Add init steps here
diff --git
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
index 0717bc3..a794d6b 100644
---
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
+++
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf
@@ -61,6 +61,7 @@
gPlatformModuleTokenSpaceGuid.PcdFabId
gPlatformModuleTokenSpaceGuid.PcdResetType
gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek
[Guids]
gEfiPlatformInfoGuid
diff --git
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInit.c
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInit.c
index ca79940..0aa9246 100644
---
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInit.c
+++
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInit.c
@@ -96,6 +96,11 @@ MinnowBoard3PostMemInitCallback (
//
BufferSize = sizeof (EFI_GUID);
PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8
*)&gPeiMinnowBoard3VbtGuid);
+
+ //
+ // Set PcdSueCreek
+ //
+ PcdSetBool (PcdSueCreek, FALSE);
//
// Add init steps here
diff --git
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf
index 90494ba..8fa5ffa 100644
---
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf
+++
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf
@@ -59,6 +59,7 @@
gPlatformModuleTokenSpaceGuid.PcdFabId
gPlatformModuleTokenSpaceGuid.PcdResetType
gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek
[Guids]
gEfiPlatformInfoGuid
diff --git
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
index d3c10b1..f0a77d1 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c
@@ -1439,6 +1439,8 @@ AcpiPlatformEntryPoint (
mGlobalNvsArea.Area->BatteryCapacity0 = 100;
mGlobalNvsArea.Area->Mmio32Base = (MmioRead32 ((UINTN)
PcdGet64 (PcdPciExpressBaseAddress) + 0xBC) & 0xFFF00000);;
mGlobalNvsArea.Area->Mmio32Length = ACPI_MMIO_BASE_ADDRESS -
mGlobalNvsArea.Area->Mmio32Base;
+ mGlobalNvsArea.Area->SueCreekEnable =
PcdGetBool(PcdSueCreek);
+
//
// Initialize IGD state by checking if IGD Device 2 Function 0 is enabled
in the chipset
//
diff --git
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
index 5e876dc..be047c1 100644
---
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+++
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -86,6 +86,7 @@
gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gPlatformModuleTokenSpaceGuid.PcdResetType
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek
[Depex]
gEfiAcpiSupportProtocolGuid AND
diff --git
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl
index b2f6f56..78416f6 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl
@@ -1,7 +1,7 @@
/** @file
ACPI GNVS
- Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -474,5 +474,11 @@
IC5S, 32, // (906) I2C5 Speed - Standard mode/Fast mode/FastPlus
mode/HighSpeed mode
IC6S, 32, // (910) I2C6 Speed - Standard mode/Fast mode/FastPlus
mode/HighSpeed mode
IC7S, 32, // (914) I2C7 Speed - Standard mode/Fast mode/FastPlus
mode/HighSpeed mode
+ SEN2, 8, // (918) EnableSen2Participant
+ PTTP, 8, // (919) PassiveThermalTripPointSen2
+ CTTP, 8, // (920) CriticalThermalTripPointSen2S3
+ HTTP, 8, // (921) HotThermalTripPointSen2
+ CRTP, 8, // (922) CriticalThermalTripPointSen2
+ SUCE, 8, // (923) SueCreekEnable: 0: disabled; 1: enabled
}
diff --git
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl
index d67b3c4..3baa88c 100644
---
a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl
+++
b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl
@@ -14,7 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
Scope (\_SB.PCI0.SPI1) {
Device (TP0) {
- Name (_HID, "SPT0001")
+ Name (_HID, "SUE1000")
Name (_DDN, "SueCreek - SPI0, CS0")
Name (_CRS, ResourceTemplate () {
SpiSerialBus (
@@ -23,15 +23,17 @@ Scope (\_SB.PCI0.SPI1) {
FourWireMode, // Full duplex
8, // Bits per word is 8 (byte)
ControllerInitiated, // Don't care
- 1000000, // 1 MHz
- ClockPolarityLow, // SPI mode 0
- ClockPhaseFirst, // SPI mode 0
+ 9600000, // 9.6 MHz
+ ClockPolarityHigh, // SPI mode 3
+ ClockPhaseSecond, // SPI mode 3
"\\_SB.PCI0.SPI1", // SPI host controller
0 // Must be 0
)
})
+
+ External(\SUCE, IntObj)
Method (_STA, 0x0, NotSerialized) {
- If (LEqual (OSYS, 2015)) {
+ If (LEqual (SUCE, 0)) {
Return (0x0)
} else {
Return (0xF)
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec
b/Platform/BroxtonPlatformPkg/PlatformPkg.dec
index 4813145..f37ceaf 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec
@@ -182,6 +182,8 @@
gPlatformModuleTokenSpaceGuid.PcdGetBoardNameFunc|0|UINT64|0x80000012
gPlatformModuleTokenSpaceGuid.PcdResetType|0x0E|UINT8|0x80000013
gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid|{ 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}|VOID*|0x80000014
+ ## This PCD used to enable or disable SueCreek
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek|FALSE|BOOLEAN|0x80000015
## MemoryCheck value for checking memory before boot OS.
## To save the boot performance, the default MemoryCheck is set to 0.
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h
index b32f334..e8319ce 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h
@@ -1,7 +1,7 @@
/** @file
Header file for Global NVS Area definition.
- Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -506,6 +506,7 @@ typedef struct {
UINT8 CriticalThermalTripPointSen2S3; ///< (920)
CriticalThermalTripPointSen2S3
UINT8 HotThermalTripPointSen2; ///< (921)
HotThermalTripPointSen2
UINT8 CriticalThermalTripPointSen2; ///< (922)
CriticalThermalTripPointSen2
+ UINT8 SueCreekEnable; ///< (923)
SueCreekEnable: 0: disabled; 1: enabled
} EFI_GLOBAL_NVS_AREA;
#pragma pack ()
--
2.10.1.windows.1
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