On Wed, Oct 25, 2017 at 06:59:44PM +0100, Ard Biesheuvel wrote:
> The ACPI hack to support the broken Synopsys IP only works for endpoints,
> not for non-trivial topologies involving switches. Given that the Linaro
> developer board has a switch soldered on, there is really no way to do
> anything useful with it when booting via ACPI. On top of that, the ITS
> can only be enabled for a single RC.
>
> So let's hide PCIe domain #0 entirely from the OS. We may be able to
> expose the USB and SATA ports at some point using another ungodly hack,
> but for now, this allows us to boot the board with unmodified installers
> and install onto NVME.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Sounds plausible, but ... Graeme?
/
Leif
> ---
> Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 264
> ++++++++++----------
> Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 44 ++--
> Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 14 +-
> 3 files changed, 161 insertions(+), 161 deletions(-)
>
> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
> b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
> index fb845d2c107e..3e231e10f7dd 100644
> --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
> @@ -25,138 +25,138 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "SNI",
> "SYNQUACR", EFI_ACPI_OEM_REVISI
> //
> // PCI Root Complex
> //
> - Device(PCI0)
> - {
> - Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> - Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name(_SEG, Zero) // PCI Segment Group number
> - Name(_BBN, Zero) // PCI Base Bus Number
> - Name(_CCA, 1) // Cache Coherency Attribute
> -
> - // PCI Routing Table
> - Name(_PRT, Package() {
> - Package () { 0xFFFF, 0, Zero, 222 }, // INTA
> - Package () { 0xFFFF, 1, Zero, 222 }, // INTB
> - Package () { 0xFFFF, 2, Zero, 222 }, // INTC
> - Package () { 0xFFFF, 3, Zero, 222 }, // INTD
> - })
> - // Root complex resources
> - Method (_CRS, 0, Serialized) {
> - Name (RBUF, ResourceTemplate () {
> - WordBusNumber ( // Bus numbers assigned to this root
> - ResourceProducer,
> - MinFixed, MaxFixed, PosDecode,
> - 0, // AddressGranularity
> - SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMinimum -
> Minimum Bus Number
> - SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMaximum -
> Maximum Bus Number
> - 0, // AddressTranslation -
> Set to 0
> - 1 // RangeLength - Number
> of Busses
> - )
> -
> - DWordMemory ( // 32-bit BAR Windows
> - ResourceProducer, PosDecode,
> - MinFixed, MaxFixed,
> - Cacheable, ReadWrite,
> - 0x00000000, // Granularity
> - SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address
> - SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address
> - 0x00000000, // Translate
> - SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length
> - )
> -
> - QWordMemory ( // 64-bit BAR Windows
> - ResourceProducer, PosDecode,
> - MinFixed, MaxFixed,
> - Cacheable, ReadWrite,
> - 0x00000000, // Granularity
> - SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Address
> - SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Address
> - 0x00000000, // Translate
> - SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length
> - )
> -
> - DWordIo ( // IO window
> - ResourceProducer,
> - MinFixed,
> - MaxFixed,
> - PosDecode,
> - EntireRange,
> - 0x00000000, // Granularity
> - SYNQUACER_PCI_SEG0_PORTIO_MIN, // Min Base Address
> - SYNQUACER_PCI_SEG0_PORTIO_MAX, // Max Base Address
> - SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate
> - SYNQUACER_PCI_SEG0_PORTIO_SIZE, // Length
> - ,
> - ,
> - ,
> - TypeTranslation
> - )
> - }) // Name(RBUF)
> -
> - Return (RBUF)
> - } // Method(_CRS)
> -
> - Device (RES0)
> - {
> - Name (_HID, "PNP0C02")
> - Name (_CRS, ResourceTemplate ()
> - {
> - Memory32Fixed (ReadWrite,
> - SYNQUACER_PCI_SEG0_CONFIG_BASE,
> - SYNQUACER_PCI_SEG0_CONFIG_SIZE)
> - })
> - }
> -
> - //
> - // OS Control Handoff
> - //
> - Name(SUPP, Zero) // PCI _OSC Support Field value
> - Name(CTRL, Zero) // PCI _OSC Control Field value
> -
> - /*
> - See [1] 6.2.10, [2] 4.5
> - */
> - Method(_OSC,4) {
> - // Check for proper UUID
> - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> - // Create DWord-adressable fields from the Capabilities
> Buffer
> - CreateDWordField(Arg3,0,CDW1)
> - CreateDWordField(Arg3,4,CDW2)
> - CreateDWordField(Arg3,8,CDW3)
> -
> - // Save Capabilities DWord2 & 3
> - Store(CDW2,SUPP)
> - Store(CDW3,CTRL)
> -
> - // Only allow native hot plug control if OS supports:
> - // * ASPM
> - // * Clock PM
> - // * MSI/MSI-X
> - If(LNotEqual(And(SUPP, 0x16), 0x16)) {
> - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> - }
> -
> - // Always allow native PME, AER (no dependencies)
> -
> - // Never allow SHPC (no SHPC controller in this system)
> - And(CTRL,0x1D,CTRL)
> -
> - If(LNotEqual(Arg1,One)) { // Unknown revision
> - Or(CDW1,0x08,CDW1)
> - }
> -
> - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were
> masked
> - Or(CDW1,0x10,CDW1)
> - }
> - // Update DWORD3 in the buffer
> - Store(CTRL,CDW3)
> - Return(Arg3)
> - } Else {
> - Or(CDW1,4,CDW1) // Unrecognized UUID
> - Return(Arg3)
> - }
> - } // End _OSC
> - } // PCI0
> +// Device(PCI0)
> +// {
> +// Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> +// Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> +// Name(_SEG, Zero) // PCI Segment Group number
> +// Name(_BBN, Zero) // PCI Base Bus Number
> +// Name(_CCA, 1) // Cache Coherency Attribute
> +//
> +// // PCI Routing Table
> +// Name(_PRT, Package() {
> +// Package () { 0xFFFF, 0, Zero, 222 }, // INTA
> +// Package () { 0xFFFF, 1, Zero, 222 }, // INTB
> +// Package () { 0xFFFF, 2, Zero, 222 }, // INTC
> +// Package () { 0xFFFF, 3, Zero, 222 }, // INTD
> +// })
> +// // Root complex resources
> +// Method (_CRS, 0, Serialized) {
> +// Name (RBUF, ResourceTemplate () {
> +// WordBusNumber ( // Bus numbers assigned to this root
> +// ResourceProducer,
> +// MinFixed, MaxFixed, PosDecode,
> +// 0, // AddressGranularity
> +// SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMinimum -
> Minimum Bus Number
> +// SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMaximum -
> Maximum Bus Number
> +// 0, // AddressTranslation
> - Set to 0
> +// 1 // RangeLength -
> Number of Busses
> +// )
> +//
> +// DWordMemory ( // 32-bit BAR Windows
> +// ResourceProducer, PosDecode,
> +// MinFixed, MaxFixed,
> +// Cacheable, ReadWrite,
> +// 0x00000000, // Granularity
> +// SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address
> +// SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address
> +// 0x00000000, // Translate
> +// SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length
> +// )
> +//
> +// QWordMemory ( // 64-bit BAR Windows
> +// ResourceProducer, PosDecode,
> +// MinFixed, MaxFixed,
> +// Cacheable, ReadWrite,
> +// 0x00000000, // Granularity
> +// SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Address
> +// SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Address
> +// 0x00000000, // Translate
> +// SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length
> +// )
> +//
> +// DWordIo ( // IO window
> +// ResourceProducer,
> +// MinFixed,
> +// MaxFixed,
> +// PosDecode,
> +// EntireRange,
> +// 0x00000000, // Granularity
> +// SYNQUACER_PCI_SEG0_PORTIO_MIN, // Min Base Address
> +// SYNQUACER_PCI_SEG0_PORTIO_MAX, // Max Base Address
> +// SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate
> +// SYNQUACER_PCI_SEG0_PORTIO_SIZE, // Length
> +// ,
> +// ,
> +// ,
> +// TypeTranslation
> +// )
> +// }) // Name(RBUF)
> +//
> +// Return (RBUF)
> +// } // Method(_CRS)
> +//
> +// Device (RES0)
> +// {
> +// Name (_HID, "PNP0C02")
> +// Name (_CRS, ResourceTemplate ()
> +// {
> +// Memory32Fixed (ReadWrite,
> +// SYNQUACER_PCI_SEG0_CONFIG_BASE,
> +// SYNQUACER_PCI_SEG0_CONFIG_SIZE)
> +// })
> +// }
> +//
> +// //
> +// // OS Control Handoff
> +// //
> +// Name(SUPP, Zero) // PCI _OSC Support Field value
> +// Name(CTRL, Zero) // PCI _OSC Control Field value
> +//
> +// /*
> +// See [1] 6.2.10, [2] 4.5
> +// */
> +// Method(_OSC,4) {
> +// // Check for proper UUID
> +//
> If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> +// // Create DWord-adressable fields from the Capabilities
> Buffer
> +// CreateDWordField(Arg3,0,CDW1)
> +// CreateDWordField(Arg3,4,CDW2)
> +// CreateDWordField(Arg3,8,CDW3)
> +//
> +// // Save Capabilities DWord2 & 3
> +// Store(CDW2,SUPP)
> +// Store(CDW3,CTRL)
> +//
> +// // Only allow native hot plug control if OS supports:
> +// // * ASPM
> +// // * Clock PM
> +// // * MSI/MSI-X
> +// If(LNotEqual(And(SUPP, 0x16), 0x16)) {
> +// And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> +// }
> +//
> +// // Always allow native PME, AER (no dependencies)
> +//
> +// // Never allow SHPC (no SHPC controller in this system)
> +// And(CTRL,0x1D,CTRL)
> +//
> +// If(LNotEqual(Arg1,One)) { // Unknown revision
> +// Or(CDW1,0x08,CDW1)
> +// }
> +//
> +// If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were
> masked
> +// Or(CDW1,0x10,CDW1)
> +// }
> +// // Update DWORD3 in the buffer
> +// Store(CTRL,CDW3)
> +// Return(Arg3)
> +// } Else {
> +// Or(CDW1,4,CDW1) // Unrecognized UUID
> +// Return(Arg3)
> +// }
> +// } // End _OSC
> +// } // PCI0
>
> Device(PCI1)
> {
> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> index bbb425f1f808..307c93c197ac 100644
> --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> @@ -39,7 +39,7 @@ typedef struct {
> EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
> SYNQUACER_ITS_NODE ItsNode;
> //SYNQUACER_SMMU_NODE Smmu;
> - SYNQUACER_RC_NODE RcNode[2];
> + SYNQUACER_RC_NODE RcNode[1];
> } SYNQUACER_IO_REMAPPING_STRUCTURE;
>
> #define __SYNQUACER_SMMU_NODE(Base, Size, Irq, NumIds) \
> @@ -91,7 +91,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
> __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
> SYNQUACER_IO_REMAPPING_STRUCTURE,
> EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
> - 3, // NumNodes
> + 2, // NumNodes
> sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
> 0 // Reserved
> }, {
> @@ -115,26 +115,26 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
> // }, {
> // PciRcNode
> {
> - {
> - {
> - EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
> - sizeof(SYNQUACER_RC_NODE), // Length
> - 0x0, // Revision
> - 0x0, // Reserved
> - 0x1, //
> NumIdMappings
> - FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdReference
> - },
> - EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, //
> CacheCoherent
> - 0x0, //
> AllocationHints
> - 0x0, // Reserved
> - EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
> - EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, //
> MemoryAccessFlags
> - EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
> - 0x0, //
> PciSegmentNumber
> - }, {
> - __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode,
> EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
> - },
> - }, {
> +// {
> +// {
> +// EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
> +// sizeof(SYNQUACER_RC_NODE), // Length
> +// 0x0, // Revision
> +// 0x0, // Reserved
> +// 0x1, //
> NumIdMappings
> +// FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), //
> IdReference
> +// },
> +// EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, //
> CacheCoherent
> +// 0x0, //
> AllocationHints
> +// 0x0, // Reserved
> +// EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
> +// EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, //
> MemoryAccessFlags
> +// EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, //
> AtsAttribute
> +// 0x0, //
> PciSegmentNumber
> +// }, {
> +// __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode,
> EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
> +// },
> +// }, {
> // PciRcNode
> {
> {
> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc
> b/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc
> index 00df5f181de3..5e18548892ae 100644
> --- a/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc
> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc
> @@ -27,7 +27,7 @@
>
> typedef struct {
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
> -
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE
> Structure[2];
> +
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE
> Structure[1];
> } EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
>
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
> @@ -39,12 +39,12 @@
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
> },
> {
> {
> - SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000,
> - 0,
> - SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> - SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> - EFI_ACPI_RESERVED_DWORD
> - }, {
> +// SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000,
> +// 0,
> +// SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> +// SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> +// EFI_ACPI_RESERVED_DWORD
> +// }, {
> SYNQUACER_PCI_SEG1_CONFIG_BASE | 0x8000,
> 1,
> SYNQUACER_PCI_SEG1_BUSNUM_MIN,
> --
> 2.11.0
>
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