On Fri, Oct 27, 2017 at 03:13:50AM +0200, Marcin Wojtas wrote:
> This patch fixes incorrect settings for UHS mode in
> SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which
> the latter was missing. This field should be set to:
>
> 0x4 for DDR52
> 0x2 for SDR50
> 0x1 for SDR25
> 0x0 for others.
>
> This way EmmcSwitchToHighSpeed function is on par with Linux
> set_uhs_signaling routine in the Xenon driver.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
> ---
> Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> index 3f73194..4d4833f 100755
> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed (
> if (IsDdr) {
> HostCtrl2 = BIT2;
> } else if (ClockFreq == 52) {
> + HostCtrl2 = BIT1;
> + } else if (ClockFreq == 26) {
> HostCtrl2 = BIT0;
> } else {
> HostCtrl2 = 0;
> --
> 2.7.4
>
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