According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.
"Bits N:0 of the limit register are
decoded by hardware as all 1s."
Cc: Jiewen Yao <jiewen....@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.z...@intel.com>
---
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
index 7147a19f538a..8f86d4cd15c0 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under
the terms and conditions of the BSD License which accompanies this
distribution.
@@ -60,7 +60,7 @@ typedef struct {
PEI Memory Layout:
- +------------------+ <=============== PHMR.Limit (Top of memory)
+ +------------------+ <=============== PHMR.Limit (+ alignment)
(Top of memory)
| Mem Resource |
| |
@@ -72,7 +72,7 @@ typedef struct {
DMA Buffer | * DMA FREE * |
| | -------------- |
V | Read/Write Buf |
- =========== +==================+ <=============== PLMR.Limit
+ =========== +==================+ <=============== PLMR.Limit (+ alignment)
| PEI allocated |
| -------------- | <------- EfiFreeMemoryTop
| * PEI FREE * |
--
2.13.3.windows.1
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