Laszlo, Thank you very much for your explanation.
> -----Original Message----- > From: Laszlo Ersek [mailto:ler...@redhat.com] > Sent: Thursday, May 3, 2018 6:52 AM > To: Roman Bacik > Cc: edk2-devel@lists.01.org; Ruiyu Ni; Vladimir Olovyannikov > Subject: Re: [edk2] [PATCH v2] MdeModulePkg/Bus: Enable ascending > resource list > > On 05/02/18 20:07, Roman Bacik wrote: > > Some processors require resource list sorted in ascending order. > > > > Cc: Ruiyu Ni <ruiyu...@intel.com> > > Cc: Vladimir Olovyannikov <vladimir.olovyanni...@broadcom.com> > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Roman Bacik <roman.ba...@broadcom.com> > > --- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > > .../Bus/Pci/PciBusDxe/PciResourceSupport.c | 43 > ++++++++++++++++++---- > > MdeModulePkg/MdeModulePkg.dec | 3 ++ > > MdeModulePkg/MdeModulePkg.dsc | 1 + > > 4 files changed, 41 insertions(+), 7 deletions(-) > > I don't understand the goal of this patch. > > (Please don't take my comments as "review" or arguments against this > patch, > I'd just like to understand the issue.) > > To my understanding, InsertResourceNode() keeps PCI resources sorted in > descending *alignment* order -- because a larger power-of-two alignment is > also suitable for a smaller power-of-two alignment. > > Say, we have a bridge with two devices behind it. The first device has one > MMIO BAR of size 32MB (requiring the same 32MB natural alignment), while > the other device has one MMIO BAR, of size 4MB (requiring the same 4MB > natural alignment). > > Ordering the resources in descending *alignment* order means that we'll > 1st > allocate the 32MB BAR, at a suitably aligned address. The important thing > is > that the end of that allocation will *also* be aligned at 32MB, hence we > can > allocate, as 2nd step, the 4MB BAR right there. No gaps needed. > > If the 4MB BAR was allocated 1st (naturally aligned), then its end address > might not be naturally aligned for becoming the base address of the > remaining 32MB BAR. Thus we might have to waste some MMIO aperture to > align the large BAR correctly. > > Here's an example output from PciBusDxe running as part of OVMF: > > > PciBus: Resource Map for Root Bridge PciRoot(0x0) [...] > > Type = Mem32; Base = 0x80000000; Length = 0x8100000; > > Alignment = > 0x3FFFFFF > > Base = 0x80000000; Length = 0x4000000; Alignment = 0x3FFFFFF; > Owner = PCI [00|02|00:14] > > Base = 0x84000000; Length = 0x4000000; Alignment = 0x3FFFFFF; > Owner = PCI [00|02|00:10] > > Base = 0x88000000; Length = 0x2000; Alignment = 0x1FFF; > > Owner = > PCI [00|02|00:18] > > Base = 0x88002000; Length = 0x1000; Alignment = 0xFFF; > > Owner = > PCI [00|07|00:14] > > Base = 0x88003000; Length = 0x1000; Alignment = 0xFFF; > > Owner = > PCI [00|06|07:10] > > Base = 0x88004000; Length = 0x1000; Alignment = 0xFFF; > > Owner = > PCI [00|05|00:14] > > Base = 0x88005000; Length = 0x1000; Alignment = 0xFFF; > > Owner = > PCI [00|03|00:14] > > [...] > > The base addresses are already sorted in ascending order; what's > descending > is the alignment -- and that seems correct, because it conserves MMIO > aperture (no gaps needed). > > Can you please explain what's wrong with this approach for your platform, > and what the desired behavior is? > > Can you post a log snippet that shows a placement that's right for your > platform? We are also patching allocation order bottom up search starting at BaseAddress. This placement is desirable and working for us after applying the submitted two patches: PciBus: Resource Map for Bridge [00|00|00] Type = PMem32; Base = 0x60000000; Length = 0x100000; Alignment = 0xFFFFF Base = 0x60000000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [01|00|00:18]; Type = PMem64 Base = 0x60020000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [01|00|01:18]; Type = PMem64 Base = 0x60040000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [01|00|02:18]; Type = PMem64 Base = 0x60060000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [01|00|03:18]; Type = PMem64 Base = 0x60080000; Length = 0x10000; Alignment = 0xFFFF; Owner = PCI [01|00|00:10]; Type = PMem64 Base = 0x60090000; Length = 0x10000; Alignment = 0xFFFF; Owner = PCI [01|00|01:10]; Type = PMem64 Base = 0x600A0000; Length = 0x10000; Alignment = 0xFFFF; Owner = PCI [01|00|02:10]; Type = PMem64 Base = 0x600B0000; Length = 0x10000; Alignment = 0xFFFF; Owner = PCI [01|00|03:10]; Type = PMem64 Base = 0x600C0000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [01|00|00:20]; Type = PMem64 Base = 0x600C1000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [01|00|01:20]; Type = PMem64 Base = 0x600C2000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [01|00|02:20]; Type = PMem64 Base = 0x600C3000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [01|00|03:20]; Type = PMem64 > > Thanks, > Laszlo Thanks, Roman _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
