It will be better to have the information that may could be added into the commit message.
1. Did you meet real issue without this patch? 2. what is the default value of IER in your case? Thanks, Star -----Original Message----- From: Duran, Leo [mailto:leo.du...@amd.com] Sent: Wednesday, June 6, 2018 5:21 AM To: Zeng, Star <star.z...@intel.com>; Dong, Eric <eric.d...@intel.com> Cc: edk2-devel@lists.01.org Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Any updates on this patch? Do you require to know my "default value of IER"? Thanks, Leo. -----Original Message----- From: edk2-devel <edk2-devel-boun...@lists.01.org> On Behalf Of Duran, Leo Sent: Friday, May 25, 2018 8:38 AM To: Zeng, Star <star.z...@intel.com>; edk2-devel@lists.01.org Cc: Dong, Eric <eric.d...@intel.com>; Zeng, Star <star.z...@intel.com> Subject: Re: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Don''t have access to test platform at this time. But will report IER value if I,m able to. Leo Get Outlook for iOS<https://aka.ms/o0ukef> ________________________________ From: Zeng, Star <star.z...@intel.com> Sent: Friday, May 25, 2018 6:13:16 AM To: Duran, Leo; edk2-devel@lists.01.org Cc: Dong, Eric; Zeng, Star Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Reviewed-by: Star Zeng <star.z...@intel.com> Just a little curious about 1. Did you meet real issue without this patch? 2. what is the default value of IER in your case? Thanks, Star -----Original Message----- From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Leo Duran Sent: Friday, May 25, 2018 3:08 AM To: edk2-devel@lists.01.org Cc: Dong, Eric <eric.d...@intel.com>; Zeng, Star <star.z...@intel.com> Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Put the UART in FIFO Polled Mode by clearing IER after setting FCR. Also, add comments to show DLAB state for registers 0 and 1. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <leo.du...@amd.com> Cc: Star Zeng <star.z...@intel.com> CC: Eric Dong <eric.d...@intel.com> --- .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index 0ccac96..6532c4d 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550 +++ .c @@ -3,6 +3,8 @@ (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR> Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR> + This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -30,10 +32,11 @@ // // 16550 UART register offsets and bitfields // -#define R_UART_RXBUF 0 -#define R_UART_TXBUF 0 -#define R_UART_BAUD_LOW 0 -#define R_UART_BAUD_HIGH 1 +#define R_UART_RXBUF 0 // LCR_DLAB = 0 +#define R_UART_TXBUF 0 // LCR_DLAB = 0 +#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1 +#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1 +#define R_UART_IER 1 // LCR_DLAB = 0 #define R_UART_FCR 2 #define B_UART_FCR_FIFOE BIT0 #define B_UART_FCR_FIFO64 BIT5 @@ -554,6 +557,11 @@ SerialPortInitialize ( SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); // + // Set FIFO Polled Mode by clearing IER after setting FCR // + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); + + // // Put Modem Control Register(MCR) into its reset state of 0x00. // SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
