On 27 June 2018 at 09:04, Ming Huang <ming.hu...@linaro.org> wrote:
> From: Jason Zhang <zhangjinso...@huawei.com>
>
> 1. During test PCIe mcs9922 UART card, the card can't
> work because the IO ATU config is overlap by Cfg0/Cfg1
> ATU address.
> 2. After adjust the ATU windows, Cfg0/Cfg1 config as below:
> Cfg0 is equal to "ECAM + (BusBase, 0, 0)"
> Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)"
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jason Zhang <zhangjinso...@huawei.com>
> Signed-off-by: Heyi Guo <heyi....@linaro.org>
> Signed-off-by: Ming Huang <ming.hu...@linaro.org>
> ---
> Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> index 55b80aa4e4..e5f66eaa4a 100644
> --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> @@ -640,11 +640,12 @@ void SetAtuConfig0RW (
> {
> UINTN RbPciBase = Private->RbPciBar;
> UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase +
> 1, 1, 0, 0) - 1;
> + UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0,
> 0, 0);
>
OK, so here you are mapping bus 0 ...
>
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
> - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW,
> (UINT32)(Private->Ecam));
> - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH,
> (UINT32)((UINT64)(Private->Ecam) >> 32));
> + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW,
> (UINT32)(Cfg0Base));
> + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH,
> (UINT32)(Cfg0Base >> 32));
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)
> MemLimit);
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
> @@ -666,12 +667,12 @@ void SetAtuConfig1RW (
> {
> UINTN RbPciBase = Private->RbPciBar;
> UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit +
> 1, 0, 0, 0) - 1;
> -
> + UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase +
> 2, 0, 0, 0);
and here you are mapping bus 2 .. buslimit.
Where are you mapping bus 1?
>
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1,
> IATU_CTRL1_TYPE_CONFIG1);
> - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW,
> (UINT32)(Private->Ecam));
> - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH,
> (UINT32)((UINT64)(Private->Ecam) >> 32));
> + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW,
> (UINT32)(Cfg1Base));
> + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH,
> (UINT32)(Cfg1Base >> 32));
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)
> MemLimit);
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
> MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
> --
> 2.17.0
>
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