This patch introduces DSDT table and adds necessary wiring in order to enable ACPI support on Armada 8040 DB.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <m...@semihalf.com> --- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 3 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf | 61 ++++ Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 5 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 330 ++++++++++++++++++++ 4 files changed, 399 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc index 3fc33d4..e2b1156 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -51,6 +51,9 @@ [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf +[Components.AARCH64] + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf + ################################################################################ # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf new file mode 100644 index 0000000..1e440f7 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR> +# Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PlatformAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt.asl + ../Fadt.aslc + ../Gtdt.aslc + ../Madt.aslc + ../Pptt.aslc + ../Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + +[BuildOptions] + *_*_*_ASLCC_FLAGS = -DARMADA8K diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc index 99e1a11..e902e9f 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc @@ -14,3 +14,8 @@ # DTB INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf + +!if $(ARCH) == AARCH64 + # ACPI support + INF RuleOverride = ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf +!endif diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl new file mode 100644 index 0000000..7c65949 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -0,0 +1,330 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00002000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00002000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xF4500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP1_USB_H0 + } + }) + } + + Device (COM1) + { + Name (_HID, "HISI0031") // _HID: Hardware ID + Name (_CID, "8250dw") // _CID: Compatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address Base + 0x00000100, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: Hardware ID + Name (_CCA, 0x01) // Cache-coherent controller + Name (_UID, 0x00) // _UID: Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: Hardware ID + Name (_CCA, 0x01) // Cache-coherent controller + Name (_UID, 0x01) // _UID: Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip76" }, + } + }) + } + + Device (RNG1) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP1_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip76" }, + } + }) + } + } +} -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
