Reviewed-by: Ruiyu Ni <ruiyu...@intel.com>
Thanks/Ray
> -----Original Message-----
> From: Zeng, Star
> Sent: Tuesday, September 11, 2018 10:04 AM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star <star.z...@intel.com>; Ni, Ruiyu <ruiyu...@intel.com>; Wang,
> Jian J <jian.j.w...@intel.com>; Wang, Fei1 <fei1.w...@intel.com>
> Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is
> set
>
> When the HSEE in the USBCMD bit is a '1' and the HSE bit in the USBSTS
> register is a '1', the xHC shall assert out-of-band error signaling to the
> host
> and assert the SERR# pin.
> To prevent masking any potential issues with SERR, this patch is to set
> USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is
> set.
>
> Cc: Ruiyu Ni <ruiyu...@intel.com>
> Cc: Jian J Wang <jian.j.w...@intel.com>
> Cc: Fei1 Wang <fei1.w...@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Star Zeng <star.z...@intel.com>
> ---
> MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41
> ++++++++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> index 5f0736a516b6..89f073e1d83f 100644
> --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
> @@ -587,6 +587,39 @@ XhcIsSysError (
> }
>
> /**
> + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable
> Bit is set.
> +
> + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller
> Reset(HCRST).
> + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
> +
> + @param Xhc The XHCI Instance.
> +
> +**/
> +VOID
> +XhcSetHsee (
> + IN USB_XHCI_INSTANCE *Xhc
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> + UINT16 XhciCmd;
> +
> + PciIo = Xhc->PciIo;
> + Status = PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint16,
> + PCI_COMMAND_OFFSET,
> + sizeof (XhciCmd),
> + &XhciCmd
> + );
> + if (!EFI_ERROR (Status)) {
> + if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {
> + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);
> + }
> + }
> +}
> +
> +/**
> Reset the XHCI host controller.
>
> @param Xhc The XHCI Instance.
> @@ -628,6 +661,14 @@ XhcResetHC (
> //
> gBS->Stall (XHC_1_MILLISECOND);
> Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET,
> XHC_USBCMD_RESET, FALSE, Timeout);
> +
> + if (!EFI_ERROR (Status)) {
> + //
> + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.
> + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
> + //
> + XhcSetHsee (Xhc);
> + }
> }
>
> return Status;
> --
> 2.7.0.windows.1
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