Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yunshan Tu <yunshan...@intel.com>
---
.../Common/Features/UsbDeviceDxe/XdciDWC.c | 12 ++++++------
.../PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c | 1 +
.../PlatformBootManagerLib/PlatformBootManager.c | 2 ++
.../PlatformSettings/PlatformDxe/PciDevice.c | 2 +-
.../PlatformPreMemPei/BootMode.c | 7 -------
.../PlatformPreMemPei/FvCallback.c | 2 +-
.../Common/PlatformSmm/Platform.c | 2 +-
.../FspmWrapperPeim/FspmWrapperPeim.c | 3 ++-
.../NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c | 4 ++--
.../Cpu/PowerManagement/Smm/PowerMgmtDts.c | 16 ++++++++--------
.../Cpu/SmmAccess/Dxe/SmmAccessDriver.c | 6 +++---
.../Cpu/SmmAccess/Pei/SmmAccessDriver.c | 4 ++--
.../BaseConfigBlockLib/BaseConfigBlockLib.c | 4 ++--
.../Library/DxeSmbiosMemoryLib/SmbiosType16.c | 4 ++--
.../Universal/Variable/RuntimeDxe/Variable.c | 4 ++--
.../Library/BaseScSpiCommonLib/SpiCommon.c | 2 +-
.../SouthCluster/Library/DxeVtdLib/DxeVtdLib.c | 1 +
.../Library/Private/DxeScHdaLib/ScHdaLib.c | 4 +++-
.../ScPciExpressHelpersLibrary.c | 4 ++--
.../Library/ScPlatformLib/ScPlatformLibrary.c | 2 +-
.../BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c | 8 ++++----
.../BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c | 2 +-
22 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c
b/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c
index 2c1e929ab7..2ade4434bd 100644
--- a/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c
+++ b/Platform/BroxtonPlatformPkg/Common/Features/UsbDeviceDxe/XdciDWC.c
@@ -22,7 +22,7 @@ UsbRegRead (
IN UINT32 Offset
)
{
- volatile UINT32 *addr = (volatile UINT32 *)(UINTN)(Base + Offset);
+ volatile UINT32 *addr = (volatile UINT32 *)((UINTN)(Base) + (UINTN)(Offset));
return *addr;
}
@@ -33,7 +33,7 @@ UsbRegWrite (
IN UINT32 val
)
{
- volatile UINT32 *addr = (volatile UINT32 *)(UINTN)(Base + Offset);
+ volatile UINT32 *addr = (volatile UINT32 *)((UINTN)(Base) + (UINTN)(Offset));
*addr = val;
}
@@ -1852,9 +1852,9 @@ DwcXdciCoreInit (
//
// Prepare a Buffer for SETUP packet
//
- LocalCoreHandle->Trbs = (DWC_XDCI_TRB *)(UINTN)((UINT32)(UINTN)
+ LocalCoreHandle->Trbs = (DWC_XDCI_TRB *)((UINTN)
LocalCoreHandle->UnalignedTrbs +
- (DWC_XDCI_TRB_BYTE_ALIGNMENT -
+ (UINTN)(DWC_XDCI_TRB_BYTE_ALIGNMENT -
((UINT32)(UINTN)LocalCoreHandle->UnalignedTrbs %
DWC_XDCI_TRB_BYTE_ALIGNMENT)));
@@ -3954,9 +3954,9 @@ UsbXdciCoreReinit (
//
// Prepare a Buffer for SETUP packet
//
- LocalCoreHandle->Trbs = (DWC_XDCI_TRB *)(UINTN)((UINT32)(UINTN)
+ LocalCoreHandle->Trbs = (DWC_XDCI_TRB *)((UINTN)
LocalCoreHandle->UnalignedTrbs +
- (DWC_XDCI_TRB_BYTE_ALIGNMENT -
+ (UINTN)(DWC_XDCI_TRB_BYTE_ALIGNMENT -
((UINT32)(UINTN)LocalCoreHandle->UnalignedTrbs %
DWC_XDCI_TRB_BYTE_ALIGNMENT)));
diff --git
a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
index c404116029..7bf54ca37d 100644
---
a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
+++
b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
@@ -89,6 +89,7 @@ PeiFspCpuPolicyInit (
VariableSize = sizeof (SYSTEM_CONFIGURATION);
SystemConfiguration = AllocateZeroPool (VariableSize);
+ ASSERT (SystemConfiguration != NULL);
Status = VariableServices->GetVariable (
VariableServices,
diff --git
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
index 5201ac080d..821ed95bc4 100644
---
a/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
+++
b/Platform/BroxtonPlatformPkg/Common/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -524,6 +524,8 @@ ProcessTcgPp (
EFI_TCG2_PHYSICAL_PRESENCE Tcg2PpData;
EFI_PHYSICAL_PRESENCE TcgPpData;
UINTN TcgPpDataSize;
+
+ Status = EFI_SUCCESS;
TcgPpData.PPRequest = TCG_PHYSICAL_PRESENCE_NO_ACTION;
Tcg2PpData.PPRequest = TCG2_PHYSICAL_PRESENCE_NO_ACTION;
diff --git
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c
index 8c1c621e0b..296638d865 100644
---
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c
+++
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PciDevice.c
@@ -443,7 +443,7 @@ PciBusEvent (
&Supports
);
- Supports &= EFI_PCI_DEVICE_ENABLE;
+ Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
//
// Work around start, PMC command register IO enable(BIT0) will always
read back as 0, though it supports IO
// so the attributes for IO will not be set, here we set it
diff --git
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BootMode.c
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BootMode.c
index c113097e55..a4182bbb1b 100644
---
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BootMode.c
+++
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/BootMode.c
@@ -424,13 +424,6 @@ SetPlatformBootMode (
CopyMem (&PlatformSetupId.SetupName, SAFE_SETUP_NAME, StrSize
(SAFE_SETUP_NAME));
PlatformSetupId.PlatformBootMode = PLATFORM_SAFE_MODE;
- } else if (0) {
- //
- // Manufacturing mode
- //
- CopyMem (&PlatformSetupId.SetupName, MANUFACTURE_SETUP_NAME, StrSize
(MANUFACTURE_SETUP_NAME));
- PlatformSetupId.PlatformBootMode = PLATFORM_MANUFACTURING_MODE;
-
} else {
//
// Default to normal mode.
diff --git
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
index d5f514a6f4..02cda154b8 100644
---
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
+++
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei/FvCallback.c
@@ -158,7 +158,7 @@ CreateVariableHobs (
return EFI_INVALID_PARAMETER;
}
- VariableStoreBase = (EFI_PHYSICAL_ADDRESS) ((UINTN) NvStorageFvHeader +
(UINTN)NvStorageFvHeader->HeaderLength);
+ VariableStoreBase = (EFI_PHYSICAL_ADDRESS) ((UINTN) NvStorageFvHeader +
(UINTN)(NvStorageFvHeader->HeaderLength));
VariableStoreHeader = (VARIABLE_STORE_HEADER *) (UINTN) VariableStoreBase;
DEBUG ((EFI_D_INFO, " VariableStoreHeader at 0x%x. VariableStoreSize =
%d\n", VariableStoreHeader, (UINTN) VariableStoreHeader->Size));
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
b/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
index 15014b020e..eccc2a67a5 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSmm/Platform.c
@@ -556,7 +556,7 @@ CpuSmmSxWorkAround(
// If C State enabled, disable it before going into S3
// The MSR will be restored back during S3 wake
//
- MsrValue &= ~B_EFI_MSR_PMG_CST_CONFIG_IO_MWAIT_REDIRECTION_ENABLE;
+ MsrValue &=
~((UINT64)B_EFI_MSR_PMG_CST_CONFIG_IO_MWAIT_REDIRECTION_ENABLE);
AsmWriteMsr64 (EFI_MSR_PMG_CST_CONFIG, MsrValue);
}
}
diff --git
a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index f403d1e214..9162fde9d1 100644
---
a/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++
b/Platform/BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -111,7 +111,7 @@ PeiFspMemoryInit (
DEBUG ((DEBUG_INFO, "PcdFspmBaseAddress = 0x%X\n", PcdGet32
(PcdFspmBaseAddress)));
DEBUG ((DEBUG_INFO, "FspmHeaderPtr = 0x%X\n", FspmHeaderPtr));
DEBUG ((DEBUG_INFO, "FspmHeaderPtr->CfgRegionSize = 0x%X\n",
FspmHeaderPtr->CfgRegionSize));
-
+ ASSERT (FspmHeaderPtr != NULL);
FspmUpdDataPtr = (FSPM_UPD *) AllocateZeroPool ((UINTN)
FspmHeaderPtr->CfgRegionSize);
ASSERT (FspmUpdDataPtr != NULL);
SourceData = (UINTN *) ((UINTN) FspmHeaderPtr->ImageBase + (UINTN)
FspmHeaderPtr->CfgRegionOffset);
@@ -119,6 +119,7 @@ PeiFspMemoryInit (
DEBUG ((DEBUG_INFO, "FspWrapperPlatformInitPreMem enter\n"));
FspmUpdDataPtr = UpdateFspUpdConfigs (PeiServices, FspmUpdDataPtr);
+ ASSERT (FspmUpdDataPtr != NULL);
FspPolicyInitPreMem (FspmUpdDataPtr);
DEBUG ((DEBUG_INFO, " NvsBufferPtr - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.NvsBufferPtr));
diff --git
a/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
b/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
index 8be6d2f8ab..f9f90630fa 100644
---
a/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
+++
b/Platform/BroxtonPlatformPkg/Common/SampleCode/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
@@ -95,8 +95,8 @@ EfiPxeBcStart (
//
// Configure block size for TFTP as a default value to handle all link
layers.
//
- Private->BlockSize = (UINTN) (Private->Ip6MaxPacketSize -
- PXEBC_DEFAULT_UDP_OVERHEAD_SIZE -
PXEBC_DEFAULT_TFTP_OVERHEAD_SIZE);
+ Private->BlockSize = (UINTN)(Private->Ip6MaxPacketSize) -
+ (UINTN)(PXEBC_DEFAULT_UDP_OVERHEAD_SIZE) -
(UINTN)(PXEBC_DEFAULT_TFTP_OVERHEAD_SIZE);
//
// PXE over IPv6 starts here, initialize the fields and list header.
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtDts.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtDts.c
index 7a2bb7f76b..d46b29b108 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtDts.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtDts.c
@@ -554,9 +554,9 @@ PackageDigitalThermalSensorEnable (
//
MsrData.Qword = AsmReadMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS);
if (mDtsValue != DTS_OUT_OF_SPEC_ONLY) {
- MsrData.Qword &= ~THERM_STATUS_LOG_MASK;
+ MsrData.Qword &= ~((UINT64)THERM_STATUS_LOG_MASK);
} else {
- MsrData.Qword &= ~B_OUT_OF_SPEC_STATUS_LOG;
+ MsrData.Qword &= ~((UINT64)B_OUT_OF_SPEC_STATUS_LOG);
}
AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS, MsrData.Qword);
@@ -570,7 +570,7 @@ PackageDigitalThermalSensorEnable (
// Only lock interrupts if in CMP mode
//
if (gSmst->NumberOfCpus > 1) {
- MsrData.Qword |= B_LOCK_THERMAL_INT;
+ MsrData.Qword |= ((UINT64)B_LOCK_THERMAL_INT);
}
AsmWriteMsr64 (EFI_MSR_MISC_PWR_MGMT, MsrData.Qword);
@@ -811,7 +811,7 @@ PackageDigitalThermalSensorSetOutOfSpecInterrupt (
// Enable Out Of Spec interrupt
//
MsrData.Qword = AsmReadMsr64 (EFI_MSR_IA32_PACKAGE_THERM_INTERRUPT);
- MsrData.Qword |= OVERHEAT_INTERRUPT_ENABLE;
+ MsrData.Qword |= ((UINT64)OVERHEAT_INTERRUPT_ENABLE);
AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_INTERRUPT, MsrData.Qword);
return EFI_SUCCESS;
@@ -970,8 +970,8 @@ PackageDigitalThermalSensorSetThreshold (
//
// Enable interrupts
//
- MsrData.Qword |= TH1_ENABLE;
- MsrData.Qword |= TH2_ENABLE;
+ MsrData.Qword |= ((UINT64)TH1_ENABLE);
+ MsrData.Qword |= ((UINT64)TH2_ENABLE);
//
// If the high temp is at TjMax (offset == 0)
@@ -979,7 +979,7 @@ PackageDigitalThermalSensorSetThreshold (
// causing many threshold crossings
//
if (MsrData.Bytes.SecondByte == 0x80) {
- MsrData.Qword &= ~TH1_ENABLE;
+ MsrData.Qword &= ~((UINT64)TH1_ENABLE);
}
AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_INTERRUPT, MsrData.Qword);
@@ -989,7 +989,7 @@ PackageDigitalThermalSensorSetThreshold (
// Clear the threshold log bits
//
MsrData.Qword = AsmReadMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS);
- MsrData.Qword &= ~THERM_STATUS_THRESHOLD_LOG_MASK;
+ MsrData.Qword &= ~((UINT64)THERM_STATUS_THRESHOLD_LOG_MASK);
AsmWriteMsr64 (EFI_MSR_IA32_PACKAGE_THERM_STATUS, MsrData.Qword);
return EFI_SUCCESS;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
index 33b302731c..7edbf1e9a0 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Dxe/SmmAccessDriver.c
@@ -139,8 +139,8 @@ Open (
Mmio64AndThenOr (MCH_BASE_ADDRESS, 0x6848, 0, 0xFF);
- SmmAccess->SmramDesc[Index].RegionState &= ~(EFI_SMRAM_CLOSED
|EFI_ALLOCATED);
- SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_OPEN;
+ SmmAccess->SmramDesc[Index].RegionState &= ~((UINT64)(EFI_SMRAM_CLOSED
|EFI_ALLOCATED));
+ SmmAccess->SmramDesc[Index].RegionState |= (UINT64)(EFI_SMRAM_OPEN);
}
SmmAccess->SmmAccess.OpenState = TRUE;
@@ -181,7 +181,7 @@ Close (
continue;
}
- SmmAccess->SmramDesc[Index].RegionState &= ~EFI_SMRAM_OPEN;
+ SmmAccess->SmramDesc[Index].RegionState &= ~((UINT64)(EFI_SMRAM_OPEN));
SmmAccess->SmramDesc[Index].RegionState |= (UINTN)(EFI_SMRAM_CLOSED
|EFI_ALLOCATED);
}
SmmAccess->SmmAccess.OpenState = FALSE;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
index 39a77f401e..0d83157261 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/SmmAccess/Pei/SmmAccessDriver.c
@@ -147,7 +147,7 @@ Open (
// END CHIPSET SPECIFIC CODE
//
SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINTN)
(~(EFI_SMRAM_CLOSED | EFI_ALLOCATED));
- SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_OPEN;
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |=
(UINT64)(EFI_SMRAM_OPEN);
SmmAccess->SmmAccess.OpenState = TRUE;
return EFI_SUCCESS;
@@ -190,7 +190,7 @@ Close (
return EFI_DEVICE_ERROR;
}
- SmmAccess->SmramDesc[DescriptorIndex].RegionState &= ~EFI_SMRAM_OPEN;
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState &=
~((UINT64)EFI_SMRAM_OPEN);
SmmAccess->SmramDesc[DescriptorIndex].RegionState |=
(UINTN)(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
SmmAccess->SmmAccess.OpenState = FALSE;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
index 3e089bf4c4..c4d7b3b619 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c
@@ -136,7 +136,7 @@ AddConfigBlock (
if (OffsetIndex == 0) {
LastUsedOffset = 0;
} else {
- LastUsedOffsetPtr = (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr +
ConfigBlkTblHdrSize + (UINTN) ((OffsetIndex - 1) * 4));
+ LastUsedOffsetPtr = (UINT32 *) ((UINTN) ConfigBlkTblAddrPtr +
ConfigBlkTblHdrSize + ((((UINTN)OffsetIndex) - 1) * 4));
LastUsedOffset = (UINT32) *LastUsedOffsetPtr;
}
*OffsetTblPtr = LastUsedOffset + ConfigBlkSize;
@@ -144,7 +144,7 @@ AddConfigBlock (
ConfigBlkTblAddrPtr->AvailableBlocks--;
ConfigBlkTblAddrPtr->AvailableSize = ConfigBlkTblAddrPtr->AvailableSize -
ConfigBlkSize;
- TempConfigBlk = (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN)
ConfigBlkTblHdrSize + (UINTN) (NumOfBlocks * 4) + (UINTN) LastUsedOffset);
+ TempConfigBlk = (CONFIG_BLOCK *) ((UINTN) ConfigBlkTblAddrPtr + (UINTN)
ConfigBlkTblHdrSize + (((UINTN)NumOfBlocks) * 4) + (UINTN) LastUsedOffset);
TempConfigBlk->Header.Size = ConfigBlkSize;
TempConfigBlk->Header.Revision = ConfigBlkAddrPtr->Header.Revision;
TempConfigBlk->Header.Guid = ConfigBlkAddrPtr->Header.Guid;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
index 194df4494a..14c9697d37 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
@@ -88,14 +88,14 @@ InstallSmbiosType16 (
}
MaxSockets = ChannelASlotNum + ChannelBSlotNum;
if (mMemInfoHob->MemInfoData.ddrType == 0) {
- if ((MAX_RANK_CAPACITY_DDR4 * SA_MC_MAX_SIDES * MaxSockets) <
SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) {
+ if ((MAX_RANK_CAPACITY_DDR4 * SA_MC_MAX_SIDES * (UINT64)(MaxSockets)) <
SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) {
SmbiosTableType16Data.MaximumCapacity = MAX_RANK_CAPACITY_DDR4 *
SA_MC_MAX_SIDES * MaxSockets;
} else {
SmbiosTableType16Data.MaximumCapacity =
SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY;
SmbiosTableType16Data.ExtendedMaximumCapacity = ((UINT64)
MAX_RANK_CAPACITY_DDR4) * SA_MC_MAX_SIDES * MaxSockets * 1024; // Convert from
KB to Byte
}
} else {
- if ((MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * MaxSockets) <
SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) {
+ if ((MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * (UINT64)(MaxSockets)) <
SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) {
SmbiosTableType16Data.MaximumCapacity = MAX_RANK_CAPACITY *
SA_MC_MAX_SIDES * MaxSockets;
} else {
SmbiosTableType16Data.MaximumCapacity =
SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
index 63834426a0..02265c14dc 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
@@ -1323,7 +1323,7 @@ Reclaim (
// Install the new variable if it is not NULL.
//
if (NewVariable != NULL) {
- if ((UINTN) (CurrPtr - ValidBuffer) + NewVariableSize >
VariableStoreHeader->Size) {
+ if ((UINTN) ((UINTN)(CurrPtr) - (UINTN)(ValidBuffer)) + NewVariableSize >
VariableStoreHeader->Size) {
//
// No enough space to store the new variable.
//
@@ -1419,7 +1419,7 @@ Reclaim (
// If volatile variable store, just copy valid buffer.
//
SetMem ((UINT8 *) (UINTN) VariableBase, VariableStoreHeader->Size, 0xff);
- CopyMem ((UINT8 *) (UINTN) VariableBase, ValidBuffer, (UINTN) (CurrPtr -
ValidBuffer));
+ CopyMem ((UINT8 *) (UINTN) VariableBase, ValidBuffer, ((UINTN)CurrPtr -
(UINTN)ValidBuffer));
Status = EFI_SUCCESS;
} else {
//
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
index c1fa73d05c..d50c179e25 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
@@ -626,7 +626,7 @@ SendSpiCmd (
// sources after the flash cycle .
//
SmiEnSave = IoRead32 ((UINTN)(UINT16)(ABase + R_SMI_EN));
- IoWrite32 ((UINTN) (UINT16) (ABase + R_SMI_EN), SmiEnSave & (UINT32)
(~B_SMI_EN_GBL_SMI));
+ IoWrite32 ((UINTN)(((UINT16)ABase) + ((UINT16)R_SMI_EN)), SmiEnSave &
(UINT32) (~B_SMI_EN_GBL_SMI));
BiosCtlSave = MmioRead8 (SpiBaseAddress + R_SPI_BCR) & B_SPI_BCR_SRC;
//
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c
index abcfee2998..bc9db39c8f 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c
@@ -547,6 +547,7 @@ UpdateDmarOnReadyToBoot (
SC_VTD_CONFIG *VtdConfig;
AcpiTableProtocol = NULL;
+ FwVol = NULL;
DmarAcpiTable = NULL;
Index = 0;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaLib.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaLib.c
index d05395eb49..7578eb1f86 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaLib.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaLib.c
@@ -226,7 +226,9 @@ NhltEndpointDump (
DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.CapabilitiesSize = %d B\n",
Endpoint->EndpointConfig.CapabilitiesSize));
DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.Capabilities:"));
for (i = 0; i < (Endpoint->EndpointConfig.CapabilitiesSize ) ; i++) {
- if (i % 16 == 0) DEBUG ((DEBUG_INFO, "\n"));
+ if (i % 16 == 0) {
+ DEBUG ((DEBUG_INFO, "\n"));
+ }
DEBUG ((DEBUG_INFO, "0x%02x, ", Endpoint->EndpointConfig.Capabilities[i]));
}
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c
index 44b62db3ff..6691b4d866 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c
@@ -1648,7 +1648,7 @@ PcieCheckPmConfig (
Operation = CalculateAspm;
} else {
Operation = ManualAspm;
- *AspmVal &= RootPortConfig->Aspm;
+ *AspmVal &= (UINT16)(RootPortConfig->Aspm);
}
//
@@ -1837,7 +1837,7 @@ PcieSetPm (
Operation = CalculateAspm;
} else {
Operation = ManualAspm;
- AspmVal &= RootPortConfig->Aspm;
+ AspmVal &= (UINT16)(RootPortConfig->Aspm);
}
//
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
index e2018e61c3..83b66fe0e0 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c
@@ -115,7 +115,7 @@ ScPmTimerStall (
// one I/O operation, and maybe generate SMI
//
while ((Counts != 0) || (RemainingTick > CurrentTick)) {
- CurrentTick = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_TMR)) &
B_ACPI_PM1_TMR_VAL;
+ CurrentTick = IoRead32 ((UINTN)(AcpiBaseAddr) + (UINTN)(R_ACPI_PM1_TMR)) &
B_ACPI_PM1_TMR_VAL;
//
// Check if timer overflow
//
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
index a7fc7a4168..4f9f221df7 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
@@ -242,7 +242,7 @@ SetHeci2Active (
DEBUG ((EFI_D_INFO, "SetHeci2Active: Setting HECI2 to active...\n"));
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN)
(mHeci_HeciBar + H_CSR);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *)
(((UINTN)mHeci_HeciBar) + ((UINTN)H_CSR));
while ((Mmio32 (mHeci_HeciBar, R_HECI_DEVIDLEC) & B_HECI_DEVIDLEC_CIP) ==
B_HECI_DEVIDLEC_CIP);
@@ -307,9 +307,9 @@ BOOLEAN HeciSendHandle (
if (mHeci_LeftSize == 0) {
return TRUE;
}
- HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *) (UINTN)
(mHeci_HeciBar + H_CSR);
- SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *) (UINTN)
(mHeci_HeciBar + SEC_CSR_HA);
- WriteBuffer = (UINT32 *) (UINTN) (mHeci_HeciBar + H_CB_WW);
+ HostControlReg = (volatile HECI_HOST_CONTROL_REGISTER *)
(((UINTN)mHeci_HeciBar) + ((UINTN)H_CSR));
+ SecControlReg = (volatile HECI_SEC_CONTROL_REGISTER *)
(((UINTN)mHeci_HeciBar) + ((UINTN)SEC_CSR_HA));
+ WriteBuffer = (UINT32 *) (((UINTN)mHeci_HeciBar) + ((UINTN)H_CB_WW));
MessageBody = (UINT32*) mHeci_Message;
MaxBuffer = HostControlReg->r.H_CBD - 0x10;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c
b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c
index 2f3d0badca..04f479e238 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SeCLib/HeciMsgLib.c
@@ -1172,7 +1172,7 @@ HeciSetSeCEnableMsg (
EFI_HECI_PROTOCOL *Heci;
HECI_FWS_REGISTER SeCFirmwareStatus;
UINTN HeciPciAddressBase;
- UINT16 TimeOut;
+ UINT32 TimeOut;
TimeOut = 0;
--
2.18.0.windows.1
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