GARRETT KIRKENDALL
SMTS Firmware Engineer | CTE
7171 Southwest Parkway, Austin, TX 78735 USA
AMD facebook | amd.com
-----Original Message-----
From: edk2-devel <edk2-devel-boun...@lists.01.org> On Behalf Of Ruiyu Ni
Sent: Friday, September 21, 2018 2:26 AM
To: edk2-devel@lists.01.org
Cc: Star Zeng <star.z...@intel.com>
Subject: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to
simplify code
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
---
.../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 ++++++++++------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index f6234b5d11..916709e276 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
#define NO_MAPPING (VOID *) (UINTN) -1
+#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)
+
//
// Lookup table for increment values based on transfer widths // @@ -122,25
+124,25 @@ CreateRootBridge (
//
// Make sure Mem and MemAbove4G apertures are valid
//
- if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
+ if (RESOURCE_VALID (Bridge->Mem)) {
ASSERT (Bridge->Mem.Limit < SIZE_4GB);
if (Bridge->Mem.Limit >= SIZE_4GB) {
return NULL;
}
}
- if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
+ if (RESOURCE_VALID (Bridge->MemAbove4G)) {
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL;
}
}
- if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
+ if (RESOURCE_VALID (Bridge->PMem)) {
ASSERT (Bridge->PMem.Limit < SIZE_4GB);
if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL;
}
}
- if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
+ if (RESOURCE_VALID (Bridge->PMemAbove4G)) {
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
return NULL;
@@ -157,11 +159,9 @@ CreateRootBridge (
// support separate windows for Non-prefetchable and Prefetchable
// memory.
//
- ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
- ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
- if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
- (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
- ) {
+ ASSERT (!RESOURCE_VALID (Bridge->PMem));
+ ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+ if (RESOURCE_VALID (Bridge->PMem) || RESOURCE_VALID
+ (Bridge->PMemAbove4G)) {
return NULL;
}
}
@@ -171,11 +171,9 @@ CreateRootBridge (
// If this bit is not set, then the PCI Root Bridge does not support
// 64 bit memory windows.
//
- ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
- ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
- if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
- (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
- ) {
+ ASSERT (!RESOURCE_VALID (Bridge->MemAbove4G));
+ ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+ if (RESOURCE_VALID (Bridge->MemAbove4G) || RESOURCE_VALID
+ (Bridge->PMemAbove4G)) {
return NULL;
}
}
--
2.16.1.windows.1
With Laszlo's comments
Reviewed-by: Garrett Kirkendall <garrett.kirkend...@amd.com>
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