On Wed, 23 Jan 2019 at 17:20, Leif Lindholm <leif.lindh...@linaro.org> wrote:
>
> On Wed, Jan 23, 2019 at 05:16:57PM +0100, Ard Biesheuvel wrote:
> > On Wed, 23 Jan 2019 at 17:13, Leif Lindholm <leif.lindh...@linaro.org>
> > wrote:
> > >
> > > On Wed, Jan 23, 2019 at 04:55:28PM +0100, Ard Biesheuvel wrote:
> > > > On Wed, 23 Jan 2019 at 16:46, Leif Lindholm <leif.lindh...@linaro.org>
> > > > wrote:
> > > > >
> > > > > On Mon, Jan 07, 2019 at 08:15:01AM +0100, Ard Biesheuvel wrote:
> > > > > > Currently, we always invalidate the TLBs entirely after making
> > > > > > any modification to the page tables. Now that we have introduced
> > > > > > strict memory permissions in quite a number of places, such
> > > > > > modifications occur much more often, and it is better for
> > > > > > performance
> > > > > > to flush only those TLB entries that are actually affected by
> > > > > > the changes.
> > > > > >
> > > > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > > > Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> > > > > > ---
> > > > > > ArmPkg/Include/Library/ArmMmuLib.h | 3 ++-
> > > > > > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 6
> > > > > > +++---
> > > > > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 16
> > > > > > +++++++---------
> > > > > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 14
> > > > > > ++++++++------
> > > > > > 4 files changed, 20 insertions(+), 19 deletions(-)
> > > > > >
> > > > > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > > b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > > index d66df3e17a02..e1fabfcbea14 100644
> > > > > > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > > @@ -129,13 +129,14 @@ STATIC
> > > > > > VOID
> > > > > > ReplaceLiveEntry (
> > > > > > IN UINT64 *Entry,
> > > > > > - IN UINT64 Value
> > > > > > + IN UINT64 Value,
> > > > > > + IN UINT64 Address
> > > > > > )
> > > > > > {
> > > > > > if (!ArmMmuEnabled ()) {
> > > > > > *Entry = Value;
> > > > > > } else {
> > > > > > - ArmReplaceLiveTranslationEntry (Entry, Value);
> > > > > > + ArmReplaceLiveTranslationEntry (Entry, Value, Address);
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > @@ -296,7 +297,8 @@ GetBlockEntryListFromAddress (
> > > > > >
> > > > > > // Fill the BlockEntry with the new TranslationTable
> > > > > > ReplaceLiveEntry (BlockEntry,
> > > > > > - ((UINTN)TranslationTable &
> > > > > > TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes |
> > > > > > TT_TYPE_TABLE_ENTRY);
> > > > > > + (UINTN)TranslationTable | TableAttributes |
> > > > > > TT_TYPE_TABLE_ENTRY,
> > > > > > + RegionStart);
> > > > >
> > > >
> > > > /me pages in the data ...
> > > >
> > > > > OK, this whole patch took a few times around the loop before I think I
> > > > > caught on what was happening.
> > > > >
> > > > > I think I'm down to the only things confusing me being:
> > > > > - The name "Address" to refer to something that is always the start
> > > > > address of a 4KB-aligned translation region.
> > > > > Is this because the function will be usable in other contexts in
> > > > > later patches?
> > > >
> > > > I could change it to VirtualAddress if you prefer.
> > > > It is only passed
> > > > for TLB maintenance which is only needed at page granularity, and the
> > > > low bits are shifted out anyway.
> > >
> > > Yeah, exactly. It would just be nice if the name reflected that. Not
> > > sure VirtualAddress does. VirtualBase? PageBase?
> > >
> >
> > Well, the argument passed in is called RegionStart, so let's just
> > stick with that.
>
> Sure. With that:
> Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
>
Thanks
GIven the discussion in the other thread regarding shareability
upgrades of barriers and TLB maintenance instructions when running
under virt, mind if I fold in the hunk below? (and add a mention to
the commit log)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
@@ -35,7 +35,7 @@
// flush translations for the target address from the TLBs
lsr x2, x2, #12
tlbi vae\el, x2
- dsb sy
+ dsb nsh
// re-enable the MMU
msr sctlr_el\el, x8
@@ -58,7 +58,7 @@ ASM_FUNC(ArmReplaceLiveTranslationEntry)
// clean and invalidate first so that we don't clobber
// adjacent entries that are dirty in the caches
dc civac, x0
- dsb ish
+ dsb nsh
EL1_OR_EL2_OR_EL3(x3)
1:__replace_entry 1
The first one reduces the scope of the tlb maintenance of a live entry
to the current CPU (and when running under virt, the hypervisor will
upgrade this to inner shareable)
The second one prevents the cache maintenance from being broadcast
unnecessarily, and will be upgraded back to ish in the same way when
running under virt.
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
