Based on KabylakeOpenBoardPkg from the following branch: https://github.com/tianocore/edk2-platforms/tree/devel-MinPlatform
Adds the DSC and build files necessary to build the N1xxWU Clevo board instance. The board follows the same build procedure as other OpenBoardPkg instances in Platform/Intel in devel-MinPlatform. Key files ========= * GitEdk2Clevo.bat - Sets up the local environment for build. * OpenBoardPkg.dsc - The N1xxWU board description file. * OpenBoardPkgConfig.dsc - Used for feature-related PCD customization. * OpenBoardPkgPcd.dsc - Used for other PCD customization. * OpenBoardPkg.fdf - The N1xxWU board flash file. * FlashMapInclude.fdf - The N1xxWU board flash map. * cln.bat - Cleans temporary files from the workspace. * prep.bat - Performs pre-build steps. * bld.bat - Performs build steps. * postbuild.bat - Performs post-build steps. * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values. Cc: Hao Wu <hao.a...@intel.com> Cc: Liming Gao <liming....@intel.com> Cc: Jiewen Yao <jiewen....@intel.com> Cc: Michael D Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kuba...@intel.com> --- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 351 ++++++++++ .../N1xxWU/OpenBoardPkgBuildOption.dsc | 155 +++++ .../N1xxWU/OpenBoardPkgConfig.dsc | 139 ++++ .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 268 ++++++++ .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 52 ++ .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 716 +++++++++++++++++++++ .../ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.bat | 85 +++ Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat | 165 +++++ Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat | 54 ++ .../Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat | 45 ++ .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 220 +++++++ Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat | 85 +++ 12 files changed, 2335 insertions(+) create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.bat create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc new file mode 100644 index 0000000000..81487ed58d --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -0,0 +1,351 @@ +## @file +# Clevo N1xxWU board description file. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## +[Defines] + # + # Set platform specific package/folder name, same as passed from PREBUILD script. + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder + # DEFINE only takes effect at R9 DSC and FDF. + # + DEFINE PLATFORM_PACKAGE = MinPlatformPkg + DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg + DEFINE PLATFORM_FSP_BIN_PACKAGE = KabylakeFspBinPkg + DEFINE PLATFORM_BOARD_PACKAGE = ClevoOpenBoardPkg + DEFINE BOARD = N1xxWU + DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) + + # + # Platform On/Off features are defined here + # + !include OpenBoardPkgConfig.dsc + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = $(PLATFORM_PACKAGE) + PLATFORM_GUID = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(PROJECT) + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = ALL + + + FLASH_DEFINITION = $(PROJECT)/OpenBoardPkg.fdf + + FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0 + DEFINE TOP_MEMORY_ADDRESS = 0x0 + + # + # Default value for OpenBoardPkg.fdf use + # + DEFINE BIOS_SIZE_OPTION = SIZE_70 + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required. + 0x60|N1xxWU + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc + +[LibraryClasses.common] + + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf + + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf + + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf + + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf + PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf + + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf + + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + + ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf + SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.inf + + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf + +# Tbt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf +!endif +# +# Silicon Init Package +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc + +[LibraryClasses.IA32] + # + # PEI phase common + # + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf +!if $(TARGET) == DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf +!endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf + +# Tbt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf +!endif +# +# Silicon Init Package +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc + +[LibraryClasses.IA32.SEC] + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + +[LibraryClasses.X64] + # + # DXE phase common + # + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf +!if $(TARGET) == DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf +!endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf + + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf + +# +# Silicon Init Package +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +[LibraryClasses.X64.DXE_SMM_DRIVER] + SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf +!if $(TARGET) == DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf +!endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf + BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf + +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf + +!include OpenBoardPkgPcd.dsc + +[Components.IA32] + +# +# Common +# +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc + + # + # FSP wrapper SEC Core + # + UefiCpuPkg/SecCore/SecCore.inf { + <LibraryClasses> + #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + +# +# Silicon +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +# +# Platform +# + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + <LibraryClasses> +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf +!else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf +!endif + } + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + <LibraryClasses> + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + <LibraryClasses> +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf +!else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf +!endif + } + + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + <LibraryClasses> + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + +# +# Security +# + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf + +# Tbt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif + +[Components.X64] + +# +# Common +# +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc + + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + + ShellBinPkg/UefiShell/UefiShell.inf + +# +# Silicon +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + +# Tbt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +!endif + +# +# Platform +# + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + +# +# OS Boot +# +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { + <LibraryClasses> +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf +!else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf +!endif + } + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { + <LibraryClasses> +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf +!else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf +!endif + } + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + <LibraryClasses> +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf +!else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf +!endif + } + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + <PcdsPatchableInModule> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 + <LibraryClasses> +!if $(TARGET) == DEBUG + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + } + +!endif + +# +# Security +# + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + +# +# Other +# + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf + +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc +!include OpenBoardPkgBuildOption.dsc diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc new file mode 100644 index 0000000000..92c757190c --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc @@ -0,0 +1,155 @@ +## @file +# Clevo N1xxWU board build option configuration. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + + + DEFINE DSC_S3_BUILD_OPTIONS = + + DEFINE DSC_CSM_BUILD_OPTIONS = + +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE + DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1 +!else + DEFINE DSC_ACPI_BUILD_OPTIONS = +!endif + + DEFINE BIOS_GUARD_BUILD_OPTIONS = + + DEFINE OVERCLOCKING_BUILD_OPTION = + + DEFINE FSP_BINARY_BUILD_OPTIONS = + + DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG + + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS = + + DEFINE RESTRICTED_OPTION = + + + DEFINE SV_BUILD_OPTIONS = + + DEFINE TEST_MENU_BUILD_OPTION = + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS = +!endif + + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS = + + + DEFINE TPM_BUILD_OPTION = + + DEFINE TPM2_BUILD_OPTION = + + DEFINE DSC_TBT_BUILD_OPTIONS = + + DEFINE DSC_DCTT_BUILD_OPTIONS = + + DEFINE EMB_BUILD_OPTIONS = + + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1 + + DEFINE DSC_KBCEMUL_BUILD_OPTIONS = + + DEFINE BOOT_GUARD_BUILD_OPTIONS = + + DEFINE SECURE_BOOT_BUILD_OPTIONS = + + DEFINE USBTYPEC_BUILD_OPTION = + + DEFINE CAPSULE_BUILD_OPTIONS = + + DEFINE PERFORMANCE_BUILD_OPTION = + + DEFINE DEBUGUSEUSB_BUILD_OPTION = + + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION = -DDISABLE_NEW_DEPRECATED_INTERFACES=1 + + DEFINE SINITBIN_BUILD_OPTION = + + DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1 + +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) + +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI +MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 + *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + + +# +# For X64 Specific Build Flag +# +GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 +MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX protection +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPLICATION] + #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc new file mode 100644 index 0000000000..b4b4763a36 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc @@ -0,0 +1,139 @@ +## @file +# Clevo N1xxWU board configuration. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[PcdsFixedAtBuild] + # + # Please select BootStage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + +[PcdsFeatureFlag] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + # + # More fine granularity control below: + # + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + +# +# BIOS build switches configuration +# + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + +# CPU + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @todo Convert TXT ASM to NASM + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE + +# SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + +# ME + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used. + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + +# +# Override some PCDs for specific build requirements. +# + # + # Disable USB debug message when Source Level Debug is enabled + # because they cannot be enabled at the same time. + # + + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + + !if $(TARGET) == DEBUG + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !else + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !endif + + !if $(TARGET) == DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc new file mode 100644 index 0000000000..bcb5ed98b4 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc @@ -0,0 +1,268 @@ +## @file +# Clevo N1xxWU board PCD configuration. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE +!if $(TARGET) == RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 + + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE + + # + # 8MB Default + # + gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 + + # + # 16MB TSEG in Debug build only. + # + !if $(TARGET) == DEBUG + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + !endif + + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + + !if $(TARGET) == RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 + !else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b + !if $(TARGET) == RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 + !else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 + !endif + + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 + + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 + + ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + + ## Specifies the AP wait loop state during POST phase. + # The value is defined as below. + # 1: Place AP in the Hlt-Loop state. + # 2: Place AP in the Mwait-Loop state. + # 3: Place AP in the Run-Loop state. + # @Prompt The AP wait loop state. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + + # + # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags + # + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions. + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \ + # that lie entirely within the expected fixed memory regions. + # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms. + # BIT3-31: Reserved + # + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + + # + # See HstiFeatureBit.h for the definition + # + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} +!endif + +[PcdsFixedAtBuild.IA32] + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 + + # Default platform supported RFC 4646 languages: (American) English + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + +[PcdsPatchableInModule.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + +!if $(TARGET) == DEBUG + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 +!endif + +[PcdsDynamicHii.X64.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout" +!endif + +[PcdsDynamicDefault] + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF + +[PcdsDynamicDefault.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + # + # Set video to native resolution as Windows 8 WHCK requirement. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + +[PcdsDynamicDefault.common.DEFAULT] + # gEfiTpmDeviceInstanceTpm20DtpmGuid + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + + # Tbt + gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2 + gBoardModuleTokenSpaceGuid.PcdExpander | 0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0 + gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1 + #gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 + gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000..a727eb3b83 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,52 @@ +## @file +# Flash map layout file for the Clevo N1xxWU board. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +#=================================================================================# +# 8 M BIOS - for FSP wrapper +#=================================================================================# +DEFINE FLASH_BASE = 0xFF800000 # +DEFINE FLASH_SIZE = 0x00800000 # +DEFINE FLASH_BLOCK_SIZE = 0x00010000 # +DEFINE FLASH_NUM_BLOCKS = 0x00000080 # +#=================================================================================# + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x00600000 # Flash addr (0xFFE00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006BC000 # Flash addr (0xFFEBC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00004000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf new file mode 100644 index 0000000000..95c1758ff3 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -0,0 +1,716 @@ +## @file +# Clevo N1xxWU board flash file. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.N1xxWU] +# +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be +# assigned with PCD values. Instead, it uses the definitions for its variety, which +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. +# +BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the FLASH Device. +Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize #The size in bytes of the FLASH Device +ErasePolarity = 1 +BlockSize = $(FLASH_BLOCK_SIZE) +NumBlocks = $(FLASH_NUM_BLOCKS) + +DEFINE SIPKG_DXE_SMM_BIN = INF +DEFINE SIPKG_PEI_BIN = INF + +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported. +# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address. +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# Fv Size can be adjusted +# +################################################################################ +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x40000 + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + # + # Be careful on CheckSum field. + # + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x01, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize +FV = FvAdvanced + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize +FV = FvSecurity + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize +FV = FvOsBoot + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize +FV = FvUefiBoot + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize +FV = FvPostMemory + +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +#Microcode +FV = FvMicrocode + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize +# FSP_S Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize +# FSP_M Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize +# FSP_T Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize +FV = FvPreMemory + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FvMicrocode] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = FALSE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = FALSE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin +} + +[FV.FvPreMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D + +INF UefiCpuPkg/SecCore/SecCore.inf +INF MdeModulePkg/Core/Pei/PeiMain.inf +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf + +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf + +[FV.FvPostMemoryUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf + +# Init Board Config PCD +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE +FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { + SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin + SECTION UI = "Vbt" +} +FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D { + SECTION RAW = MdeModulePkg/Logo/Logo.bmp +} +!endif # PcdPeiDisplayEnable + +[FV.FvPostMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917 + +FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvPostMemoryUncompact + } +} + +[FV.FvUefiBootUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf + +INF UefiCpuPkg/CpuDxe/CpuDxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf +INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + +INF ShellBinPkg/UefiShell/UefiShell.inf + +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + +[FV.FvUefiBoot] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf + +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf + +INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf + +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + +!endif + +[FV.FvLateSilicon] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf + +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf + +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf + +INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf +INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf + +!endif + +[FV.FvOsBoot] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A + +FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + +FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvLateSilicon + } + } + +[FV.FvSecurityPreMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf + +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + +[FV.FvSecurityPostMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + +[FV.FvSecurityLate] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf + +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + +INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf + +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!endif + +[FV.FvSecurity] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF + +FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE = FvSecurityPreMemory + } + +FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityPostMemory + } + } + +FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +[FV.FvAdvancedPreMem] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305 + +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif + +[FV.FvAdvancedPostMem] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27 + +[FV.FvAdvancedLate] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D + +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf +!endif + +[FV.FvAdvanced] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A + +FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 { + SECTION FV_IMAGE = FvAdvancedPreMem + } + +FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA { + SECTION FV_IMAGE = FvAdvancedPostMem + } + +FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedLate + } + } + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf + diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.bat new file mode 100644 index 0000000000..9a34a9a2d2 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.bat @@ -0,0 +1,85 @@ +@REM @file +@REM +@REM Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@echo off + +pushd ..\..\..\..\..\ + +@REM Set WORKSPACE environment. +set WORKSPACE=%cd% +echo. +echo Set WORKSPACE as: %WORKSPACE% +echo. + +@REM Check whether Git has been installed and been added to system path. +git --help >nul 2>nul +if %ERRORLEVEL% NEQ 0 ( + echo. + echo The 'git' command is not recognized. + echo Please make sure that Git is installed and has been added to system path. + echo. + goto :EOF +) + +@REM Create the Conf directory under WORKSPACE +if not exist %WORKSPACE%\Conf ( + mkdir Conf +) + +@REM Set other environments. +@REM Basic Rule: +@REM Platform override Silicon override Core +@REM Source override Binary + +set PACKAGES_PATH=%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%WORKSPACE%\FSP;%WORKSPACE%\edk2;%WORKSPACE% +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 + +@if not defined PYTHON_HOME ( + @if exist C:\Python27 ( + set PYTHON_HOME=C:\Python27 + ) +) + +set EDK_SETUP_OPTION= +@rem if python is installed, disable the binary base tools. +if defined PYTHON_HOME ( + set EDK_TOOLS_BIN= + set EDK_SETUP_OPTION=--nt32 +) +pushd %WORKSPACE%\edk2 +call edksetup.bat %EDK_SETUP_OPTION% +popd +pushd %WORKSPACE% +@rem if python is installed, nmake BaseTools source and enable BaseTools source build +@if defined PYTHON_HOME ( + nmake -f %BASE_TOOLS_PATH%\Makefile +) +popd + +set openssl_path=%WORKSPACE% + +popd + +goto :EOF + +:Help +echo. +echo Usage: +echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] (optional) +echo. +echo -w A absolute/relative path to be the workspace. +echo Default value is the current directory. +echo. +echo -b The branch name of the repository. Currently, only master, udk2015, +echo trunk (same as master) and bp13 (same as udk2015) are supported. +echo Default value is master. +echo. diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat new file mode 100644 index 0000000000..a1b512b428 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat @@ -0,0 +1,165 @@ +@REM @file +@REM +@REM Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +:: Useage: bld [/s] [/f <FEATURE_PCD_NAME> <FALSE or TRUE>] [/r] +:: +:: For a given build command, 3 options may be passed into this batch file via command prompt: +:: 1) /s = Redirects all output to a file called EDK2.log(Prep.log must be existed), which will be located at the root. +:: 2) /f = Defines the passing in of a single override to a feature PCD that is used in the platform +:: DSC file. If this parameter is used, it is to be followed immediately after by both the feature +:: pcd name and value. FeaturePcd is the full PCD name, like gMinPlatformPkgTokenSpaceGuid.PcdOptimizeCompilerEnable +:: 3) /r = Useful for faster rebuilds when no changes have been made to .inf files. Passes -u to +:: build.exe to skip the generation of makefiles. +:: 4) rom = Build Bios.rom only and building SPIs will be skipped. +:: + +@echo on + +cd %WORKSPACE% + +@REM +@REM Build FSP Binary +@REM +@if not defined FSP_BINARY_BUILD goto :SkipFspBinaryBuild +@if %FSP_BINARY_BUILD% EQU FALSE goto :SkipFspBinaryBuild +@set FSP_BUILD_PARAMETER=/d +@set FSP_PKG_NAME=KabylakeFspPkg +@if /I "%TARGET%" == "RELEASE" ( + @if "%FSP_TEST_RELEASE%"=="TRUE" ( + set FSP_BUILD_PARAMETER=/tr + ) else ( + set FSP_BUILD_PARAMETER=/r + ) +) + +@if %FSP_WRAPPER_BUILD% EQU FALSE goto :BldEnd +:SkipFspBinaryBuild + +@if %FSP_WRAPPER_BUILD% EQU FALSE goto :SkipPatchFspBinFvsBaseAddress +del /f %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased*.fd + +cd %WORKSPACE% + +if exist %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc attrib -r %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc +@call %PYTHON_HOME%\python.exe %WORKSPACE_PLATFORM%\%PLATFORM_PACKAGE%\Tools\Fsp\RebaseAndPatchFspBinBaseAddress.py %WORKSPACE_PLATFORM%\%PROJECT%\Include\Fdf\FlashMapInclude.fdf %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg Fsp.fd %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc 0x0 + +@if %ERRORLEVEL% NEQ 0 ( + @echo !!! ERROR:RebaseAndPatchFspBinBaseAddress failed!!! + set SCRIPT_ERROR=1 + goto :BldFail +) + +cd %WORKSPACE% + +copy /y /b %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S.fd+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_M.fd+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_T.fd %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased.fd +:SkipPatchFspBinFvsBaseAddress + + +@SET SILENT_MODE=FALSE +@SET REBUILD_MODE= +@SET BUILD_ROM_ONLY= + +:: Loop through arguements until all are processed + +:BUILD_FLAGS_LOOP + +@if "%~1" == "" goto BUILD_FLAGS_LOOP_DONE + +@if "%~1" == "/f" ( + shift + goto BUILD_FLAGS_LOOP +) +@if "%~1" == "/s" ( + SET SILENT_MODE=TRUE + shift + goto BUILD_FLAGS_LOOP +) +@if "%~1" == "/r" ( + SET REBUILD_MODE=-u + shift + goto BUILD_FLAGS_LOOP +) +@if "%~1" == "rom" ( + SET BUILD_ROM_ONLY=rom + shift + goto BUILD_FLAGS_LOOP +) +:: Unknown build flag. +shift +goto BUILD_FLAGS_LOOP +:BUILD_FLAGS_LOOP_DONE + +:: Output the build variables the user has selected. + +@echo. +@echo User Selected build options: +@echo SILENT_MODE = %SILENT_MODE% +@echo REBUILD_MODE = %REBUILD_MODE% +@echo BUILD_ROM_ONLY = %BUILD_ROM_ONLY% +@echo. + +@if %SILENT_MODE% EQU TRUE goto BldSilent + +call build -n %NUMBER_OF_PROCESSORS% %REBUILD_MODE% %EXT_BUILD_FLAGS% + +@if %ERRORLEVEL% NEQ 0 goto BldFail +@echo. +@echo Running postbuild.bat to complete the build process. +@echo. +call %WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat %BUILD_ROM_ONLY% +@if %SCRIPT_ERROR% EQU 1 goto BldFail +@goto BldSuccess + +:BldSilent +@if exist Build.log del Build.log + +@echo. > Build.log +@echo ************************************************************************ >> Build.log +@echo *********** Build.bat is launched here *********** >> Build.log +@echo ************************************************************************ >> Build.log +@echo. >> Build.log + +call build -n %NUMBER_OF_PROCESSORS% %REBUILD_MODE% %EXT_BUILD_FLAGS% 1>>Build.log 2>&1 + +@if %ERRORLEVEL% NEQ 0 goto BldFail +@echo. >> Build.log +@echo Running postbuild.bat to complete the build process. >> Build.log +@echo. >> Build.log +@call %WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat %BUILD_ROM_ONLY% 1>>Build.log 2>&1 +@If %SCRIPT_ERROR% EQU 1 goto BldFail + +:BldSuccess +@echo. +@echo TARGET: %TARGET% +@echo TOOL_CHAIN_TAG: %TOOL_CHAIN_TAG% +@echo BIOS location: %BUILD_DIR%\FV +@echo. +@echo The EDKII BIOS build has successfully completed! +@echo. +@REM + +@goto BldEnd + +:BldFail +cd %WORKSPACE_PLATFORM%\%PROJECT% +@echo. +@echo The EDKII BIOS Build has failed! +@echo. +@exit /b 1 + +:BldEnd +@if %SILENT_MODE% EQU TRUE ( + @if exist EDK2.log del EDK2.log + @if exist Prep.log if exist Build.log copy Prep.log+Build.log EDK2.log +) + +cd %WORKSPACE_PLATFORM%\%PROJECT% \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat new file mode 100644 index 0000000000..d4d98dd135 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat @@ -0,0 +1,54 @@ +@REM @file +@REM +@REM Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@echo off +echo. +echo Run build cleanall... +echo. + +cd .. + +if not defined WORKSPACE set WORKSPACE=%cd% +if not defined WORKSPACE_PLATFORM set WORKSPACE_PLATFORM=%cd% +if not defined WORKSPACE_SILICON set WORKSPACE_SILICON=%cd% + +REM build cleanall + +echo. +echo Directories to clean... +echo. + +if exist %WORKSPACE%\build rmdir /q /s %WORKSPACE%\build +if exist %WORKSPACE%\conf\.cache rmdir /q /s %WORKSPACE%\conf\.cache + +echo. +echo Files to clean... +echo. + +if exist %WORKSPACE%\edk2.log del %WORKSPACE%\edk2.log +if exist %WORKSPACE%\Conf\build_rule.txt del %WORKSPACE%\Conf\build_rule.txt +if exist %WORKSPACE%\Conf\FrameworkDatabase.db del %WORKSPACE%\Conf\FrameworkDatabase.db +if exist %WORKSPACE%\Conf\target.txt del %WORKSPACE%\Conf\target.txt +if exist %WORKSPACE%\Conf\tools_def.txt del %WORKSPACE%\Conf\tools_def.txt +@REM *.c.c is generated by Catalog Debug feature across code tree. +@REM +del /s *.c.c > nul 2>&1 + +cd %WORKSPACE_PLATFORM%\%PROJECT% + +del /f /q Prep.log > nul 2>&1 +del /f /q ..\Build.log > nul 2>&1 + +echo. +echo All done... +echo. +@echo on diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat new file mode 100644 index 0000000000..70be663897 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat @@ -0,0 +1,45 @@ +@REM @file +@REM +@REM Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@REM # +@REM # Module Name: +@REM # +@REM # postbuild.bat +@REM # +@REM # Abstract: +@REM # +@REM # Post build script. +@REM # +@REM #--*/ + +@set SCRIPT_ERROR=0 + +@if /I not "%0" == "%WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat" ( + if /I not "%0" == "%WORKSPACE_PLATFORM%\%PROJECT%\postbuild" ( + echo. + echo !!! ERROR !!! This postbuild.bat must run under workspace root using "%WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat" !!! + echo. + set SCRIPT_ERROR=1 + goto :EOF + ) +) + +@cd %WORKSPACE_PLATFORM% + +@cd %WORKSPACE% + +@if %FSP_WRAPPER_BUILD% EQU TRUE ( + del /f %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased*.fd +) + +@if %FSP_WRAPPER_BUILD% EQU TRUE exit /b + diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat new file mode 100644 index 0000000000..c09d2d5b16 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat @@ -0,0 +1,220 @@ +@REM @file +@REM Pre build script. +@REM +@REM Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +cd .. + +@REM +@REM Set build capsule flag with default being OFF +@REM + +@set CAPSULE_BUILD=0 + +@if /I "%2" == "TRUE" ( + @set CAPSULE_BUILD=1 + goto StartCapsulePrep +) + +:StartCapsulePrep +@REM +@REM Define platform specific environment variables. +@REM +if not defined WORKSPACE_PLATFORM set WORKSPACE_PLATFORM=%WORKSPACE%\edk2-platforms\Platform\Intel +if not defined WORKSPACE_SILICON set WORKSPACE_SILICON=%WORKSPACE%\edk2-platforms\Silicon\Intel +if not defined WORKSPACE_PLATFORM_BIN set WORKSPACE_PLATFORM_BIN=%WORKSPACE%\edk2-non-osi\Platform\Intel +if not defined WORKSPACE_SILICON_BIN set WORKSPACE_SILICON_BIN=%WORKSPACE%\edk2-non-osi\Silicon\Intel +if not defined WORKSPACE_FSP_BIN set WORKSPACE_FSP_BIN=%WORKSPACE%\FSP +if not defined WORKSPACE_CORE set WORKSPACE_CORE=%WORKSPACE%\edk2 +if not defined PLATFORM_PACKAGE set PLATFORM_PACKAGE=MinPlatformPkg +if not defined PLATFORM_BOARD_PACKAGE set PLATFORM_BOARD_PACKAGE=ClevoOpenBoardPkg +if not defined BOARD set BOARD=N1xxWU +if not defined PROJECT set PROJECT=%PLATFORM_BOARD_PACKAGE%\%BOARD% + +@set SCRIPT_ERROR=0 + +@set CATALOG_DEBUG=0 + +@REM Set basic environment. +@echo. +@echo Prebuild: Run edksetup.bat batch file. +@echo. +@if %CATALOG_DEBUG% == 0 ( + @del Conf\build_rule.txt +) +cd %WORKSPACE_CORE% +@call edksetup.bat +cd %WORKSPACE% +@set EFI_SOURCE=%WORKSPACE_CORE% + +@REM +@REM Setup Visual Studio environment. Order of precedence is 2012, 2013, 2010 and then 2008. +@REM +@REM NOTE: To override precedence set TOOL_CHAIN_TAG before calling prep.bat. +@REM Example: set TOOL_CHAIN_TAG=VS2008 +@REM + +@REM Check if tool chain has not been selected and Visual Studio 2014 is installed. +@if not defined TOOL_CHAIN_TAG ( + if defined VS140COMNTOOLS ( + set TOOL_CHAIN_TAG=VS2015 + ) +) + +@REM If Visual Studio 2014 is selected by priority or by preference, setup the environment variables. +@if /I "%TOOL_CHAIN_TAG%"=="VS2015" ( + echo. + echo Prebuild: Set the VS2015 environment. + echo. + if not defined VSINSTALLDIR call "%VS140COMNTOOLS%\vsvars32.bat" + if /I "%VS140COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 14.0\Common7\Tools\" ( + set TOOL_CHAIN_TAG=VS2015 + ) else ( + set TOOL_CHAIN_TAG=VS2015x86 + ) +) + +@REM Check if tool chain has not been selected and Visual Studio 2013 is installed. +@if not defined TOOL_CHAIN_TAG ( + if defined VS120COMNTOOLS ( + set TOOL_CHAIN_TAG=VS2013 + ) +) + +@REM If Visual Studio 2013 is selected by priority or by preference, setup the environment variables. +@if /I "%TOOL_CHAIN_TAG%"=="VS2013" ( + echo. + echo Prebuild: Set the VS2013 environment. + echo. + if not defined VSINSTALLDIR call "%VS120COMNTOOLS%\vsvars32.bat" + if /I "%VS120COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 12.0\Common7\Tools\" ( + set TOOL_CHAIN_TAG=VS2013 + ) else ( + set TOOL_CHAIN_TAG=VS2013x86 + ) +) + +@REM If no supported version of Visual Studio was detected, return an error. +@if not defined TOOL_CHAIN_TAG ( + echo. + echo !!! ERROR !!! Visual Studio not installed correctly!!! + echo. + set SCRIPT_ERROR=1 + goto :EndPreBuild +) + +echo Show CL revision +cl + +@REM Set build TARGET. +@if /I "%1" == "" ( + set TARGET=DEBUG + set TARGET_SHORT=D +) else if /I "%1" == "DEBUG" ( + set TARGET=DEBUG + set TARGET_SHORT=D +) else if /I "%1" == "TEST_RELEASE" ( + set TARGET=RELEASE + set TARGET_SHORT=R +) else if /I "%1" == "RELEASE" ( + set TARGET=RELEASE + set TARGET_SHORT=R +) else if /I "%1" == "RELEASE_PDB" ( + set TARGET=RELEASE + set TARGET_SHORT=R +) else ( + echo. + echo !!! ERROR !!! Incorrect TARGET option for prebuild.bat. !!! + echo. + set SCRIPT_ERROR=1 + goto :EndPreBuild +) + +@set BUILD_DIR_PATH=%WORKSPACE%\Build\%PROJECT%\%TARGET%_%TOOL_CHAIN_TAG% +@set BUILD_DIR=Build\%PROJECT%\%TARGET%_%TOOL_CHAIN_TAG% +@set BUILD_X64=%BUILD_DIR_PATH%\X64 +@set BUILD_IA32=%BUILD_DIR_PATH%\IA32 + + +@echo. +@echo Prebuild: Set build environment. +@echo. +@if not exist %BUILD_DIR_PATH% ( + mkdir %BUILD_DIR_PATH% +) + +@findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_CONF" %WORKSPACE%\Conf\target.txt > %BUILD_DIR_PATH%\target.txt +@echo ACTIVE_PLATFORM = %WORKSPACE_PLATFORM%/%PLATFORM_BOARD_PACKAGE%/%BOARD%/OpenBoardPkg.dsc >> %BUILD_DIR_PATH%\target.txt +@echo TARGET = %TARGET% >> %BUILD_DIR_PATH%\target.txt +@echo TARGET_ARCH = IA32 X64 >> %BUILD_DIR_PATH%\target.txt +@echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG% >> %BUILD_DIR_PATH%\target.txt +@echo BUILD_RULE_CONF = Conf/build_rule.txt >> %BUILD_DIR_PATH%\target.txt +@move /Y %BUILD_DIR_PATH%\target.txt Conf + +@if %CAPSULE_BUILD% == 1 ( + goto EndCapsulePrep +) + +@REM +@REM Set %FSP_WRAPPER_BUILD% +@REM +@set FSP_WRAPPER_BUILD=TRUE + +@if %FSP_WRAPPER_BUILD% EQU TRUE ( + @REM Create dummy Fsp_Rebased_S_padded.fd to build the BiosInfo.inf if it is wrapper build, due to the SECTION inclusion + echo "" > %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S_padded.fd + attrib -r %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S_padded.fd +) + +@REM +@REM Set %PERFORMANCE_BUILD% +@REM +@set PERFORMANCE_BUILD=FALSE + +@REM +@REM Set %FSP_BINARY_BUILD% and %FSP_TEST_RELEASE% +@REM +@set FSP_BINARY_BUILD=FALSE +@set FSP_TEST_RELEASE=FALSE + +@if "FSP_BINARY_BUILD"=="TRUE" ( + @if %FSP_WRAPPER_BUILD% EQU FALSE goto :EndPreBuild +) + +@if not exist %BUILD_X64% ( + mkdir %BUILD_X64% +) + +@set SECURE_BOOT_ENABLE=FALSE + +@REM +@REM Skip BIOS_SIZE_OPTION if it is predefined +@REM +@if NOT "%BIOS_SIZE_OPTION%" == "" goto BiosSizeDone + +@set BIOS_SIZE_OPTION= + +@REM default size option is 7M +@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_70 + +:BiosSizeDone +@echo BIOS_SIZE_OPTION=%BIOS_SIZE_OPTION% + +@echo EFI_SOURCE = %EFI_SOURCE% +@echo TARGET = %TARGET% +@echo TARGET_ARCH = IA32 X64 +@echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG% +@echo WORKSPACE = %WORKSPACE% +@echo WORKSPACE_CORE = %WORKSPACE_CORE% +@echo EXT_BUILD_FLAGS = %EXT_BUILD_FLAGS% +@echo. +:EndPreBuild +cd %WORKSPACE_PLATFORM%\%PROJECT% diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat new file mode 100644 index 0000000000..d307e8eee0 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat @@ -0,0 +1,85 @@ +@REM @file +@REM +@REM Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@echo OFF +@set PrepRELEASE=DEBUG +@set SILENT_MODE=FALSE +@set CapsuleBuild=FALSE + +@set EXT_CONFIG_CLEAR= +@set EXT_BUILD_FLAGS= + +:CmdLineParse +if "" == "%1" ( + goto Continue +) else if "r" == "%1" ( + set PrepRELEASE=RELEASE +) else if "tr" == "%1" ( + set PrepRELEASE=TEST_RELEASE +) else if "rp" == "%1" ( + set PrepRELEASE=RELEASE_PDB +) else if "s" == "%1" ( + set SILENT_MODE=TRUE +) else if "help" == "%1" ( + goto PrepHelp +) else ( + echo Invalid input arguments: %1 + echo. + goto PrepHelp +) +SHIFT +goto CmdLineParse + +:PrepHelp +@echo Preparation for BIOS build. +@echo. +@echo prep [r][rp][s][help] +@echo. +@echo r To do release build. Default is debug build. See note 1 +@echo rp To do release build with Symbols - For source level debugging. See note 1 +@echo s To build in silent mode. . See note 1 +@echo. +@echo 1) Re-running prep without these arguments cannot be used for +@echo incremental build. Hence, these inputs must be supplied each time +@echo prep are desired to be re-run. +@echo. +goto PrepDone + +:Continue +@echo ============================================== + +if exist %WORKSPACE%\Prep.log del %WORKSPACE%\Prep.log + +:PrepReleaseCheck + +@if %SILENT_MODE% EQU TRUE goto BldSilent + +call prebuild.bat %PrepRelease% %CapsuleBuild% +goto PrePrepDone + +:BldSilent +@echo ************************************************************************ >> %WORKSPACE%\Prep.log +@echo *********** Prebuild.bat is launched here *********** >> %WORKSPACE%\Prep.log +@echo ************************************************************************ >> %WORKSPACE%\Prep.log +call prebuild.bat %PrepRelease% %CapsuleBuild% 1>>%WORKSPACE%\Prep.log 2>&1 + +:PrePrepDone +@If %SCRIPT_ERROR% EQU 1 goto PrepFail +@goto PrepDone + +:PrepFail +@echo. +@echo !! The EDKII BIOS build has failed in prep! +@echo. +@exit /b 1 + +:PrepDone \ No newline at end of file -- 2.16.2.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
