Hi Tiger,

The ARM recommendation to manage secondary CPUs (the primary CPU is the CPU
that runs UEFI and starts your OS kernel) is to use PSCI (Power State
Coordination Interface -
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0022b/index.h
tml).
PSCI uses SMCs (Secure Memory Calls) to bring up secondary CPUs (CPU_UP /
CPU_DOWN). This code runs in Secure World while UEFI runs in Non-Secure
World.

For the story... I started to implement PSCI support in Tianocore source
code (in ArmPlatformPkg/Sec). But the EDK2 framework (PCD/Library/INF/FDF
etc) had made the code quite hard to maintain.
So, I wrote a new secure firmware framework project to handle this support.
This firmware is not Open Source (available in binary format for TC2 only).
A new project has been started by ARM Ltd last month. It is an Open Source
implementation of the Trusted/Secure Firmware:
https://github.com/ARM-software/arm-trusted-firmware
Unfortunately at this stage, 32bit is not supported (only AArch64 is
supported). And as far as I know there is no plan to add 32bit support by
ARM Ltd in the short term.

The current ArmPlatformPkg/Sec has support to hold the secondary cores in
WFI. But it does not support PSCI. The current support might be sufficient
enough for you at this stage.

Thanks,
Olivier

> -----Original Message-----
> From: tiger...@viatech.com.cn [mailto:tiger...@viatech.com.cn]
> Sent: 04 December 2013 01:51
> To: edk2-devel@lists.sourceforge.net
> Cc: Olivier Martin
> Subject: [edk2] SEC code support big.LITTLE tech?
> 
> Hi, Oliver:
> Does current ArmPlatformPackage's sec code support big.LITTLE tech?
> Such as :
> An ARM SOC --- with 4 Cores Cortex-A15, 4 Cores Cortex-A7
> 
> So, if sec code support big.LITTLE tech, how does it let one core as
> boot strap cpu, others go into wfe(or other sleeping state)?
> 
> Best wishes,





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