Hi Olivier,
I modified the Stacks so that the typedef is UINT64;
for pointing to System Memory outside of the addressable region accessable
via UINT32. This is very similar to the System Memory changes you made
regarding System Memory base address earlier. I can across this issue when
migrating to our silicon memory map, which has the stacks in DRAM outside
of the addressable range afforded by a UINT32 typedef. Please suggest
changes or considerations I might have overlooked. I tested this on
AARCH64 across multiple memory regions; including the RTSM SRAM locations.
Thanks,
Steve
From fe3fe86ec70945cc8612b5c63b62764652a7a415 Mon Sep 17 00:00:00 2001
From: Steven Kinney <steven.kin...@amd.com>
Date: Fri, 21 Feb 2014 08:26:21 -0600
Subject: [PATCH] ArmPlatformPkg: PcdCPUCoreSecStackBase and
PcdCPUCoresStackBase: UINT64
Modify the type defintion for PcdCPUCoreSecStackBase and PcdCPUCoresStackBase
to allow for stacks that reside in upper System Memory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Steven Kinney <steven.kin...@amd.com>
---
ArmPlatformPkg/ArmPlatformPkg.dec | 4 ++--
.../Pei/PeiArmPlatformGlobalVariableLib.c | 6 +++---
ArmPlatformPkg/PrePeiCore/MainMPCore.c | 2 +-
ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 114c591..71301f4 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -63,12 +63,12 @@
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
# Stack for CPU Cores in Secure Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
# Stack for CPU Cores in Non Secure Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
diff --git a/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c b/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c
index df3e129..2ffbdbe 100644
--- a/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c
+++ b/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c
@@ -34,7 +34,7 @@ ArmPlatformGetGlobalVariable (
// Ensure the Global Variable Size have been initialized
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));
- GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
+ GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
if (VariableSize == 4) {
*(UINT32*)Variable = ReadUnaligned32 ((CONST UINT32*)(GlobalVariableBase + VariableOffset));
@@ -57,7 +57,7 @@ ArmPlatformSetGlobalVariable (
// Ensure the Global Variable Size have been initialized
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));
- GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
+ GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
if (VariableSize == 4) {
WriteUnaligned32 ((UINT32*)(GlobalVariableBase + VariableOffset), *(UINT32*)Variable);
@@ -78,7 +78,7 @@ ArmPlatformGetGlobalVariableAddress (
// Ensure the Global Variable Size have been initialized
ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize));
- GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
+ GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize);
return (VOID*)(GlobalVariableBase + VariableOffset);
}
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 9bfc990..f849d85 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -124,7 +124,7 @@ PrimaryMain (
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
// the base of the primary core stack
PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);
- TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
// Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 1abefae..9cae823 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -53,7 +53,7 @@ CreatePpiList (
ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
// Copy the Common and Platform PPis in Temporrary Memory
- ListBase = PcdGet32 (PcdCPUCoresStackBase);
+ ListBase = PcdGet64 (PcdCPUCoresStackBase);
CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));
CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
@@ -153,7 +153,7 @@ PrePeiCoreGetGlobalVariableMemory (
{
ASSERT (GlobalVariableBase != NULL);
- *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) +
+ *GlobalVariableBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) +
(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -
(UINTN)PcdGet32 (PcdPeiGlobalVariableSize);
--
1.7.9.5
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