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so please use this one to reply with feedback. Sorry about that !


OvmfPkg/Library/AcpiTimerLib: Access power mgmt regs based on host bridge type

Pick the appropriate bus:dev.fn for accessing ACPI power management
registers (00:01.3 on PIIX4 vs. 00:1f.0 on Q35) based on the DID of
the host bridge (assumed always present at 00:00.0).

With this patch, OVMF can boot QEMU's "-machine q35" x86 machine type.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gabriel Somlo <[email protected]>
---

I can boot Fedora20 Live with this patch applied on top of Reza's
SATA series:

http://sourceforge.net/p/edk2/mailman/message/32743992/

using the following command line:

bin/qemu-system-x86_64 -machine q35 \
  -device ide-drive,bus=ide.2,drive=HDC \
  -drive id=HDC,if=none,snapshot=on,file=Fedora-Live-Desktop-x86_64-20-1.iso \
  -enable-kvm -m 2048 -usb -device usb-kbd -device usb-mouse \
  -bios OVMF.fd

Any comments/suggestions/feedback much appreciated.

Thanks much,
   Gabriel

 OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c | 59 ++++++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c 
b/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c
index c644128..f824283 100644
--- a/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c
@@ -43,11 +43,66 @@
     )
 
 //
+// PCI Location of Q35 Power Management PCI Configuration Registers
+//
+#define Q35_POWER_MANAGEMENT_BUS       0x00
+#define Q35_POWER_MANAGEMENT_DEVICE    0x1f
+#define Q35_POWER_MANAGEMENT_FUNCTION  0x00
+
+//
+// Macro to access Q35 Power Management PCI Configuration Registers
+//
+#define Q35_PCI_POWER_MANAGEMENT_REGISTER(Register) \
+  PCI_LIB_ADDRESS (                                 \
+    Q35_POWER_MANAGEMENT_BUS,                       \
+    Q35_POWER_MANAGEMENT_DEVICE,                    \
+    Q35_POWER_MANAGEMENT_FUNCTION,                  \
+    Register                                        \
+    )
+
+//
+// PCI Location of Host Bridge PCI Configuration Registers
+//
+#define HOST_BRIDGE_BUS       0x00
+#define HOST_BRIDGE_DEVICE    0x00
+#define HOST_BRIDGE_FUNCTION  0x00
+
+//
+// Macro to access Host Bridge Configuration Registers
+//
+#define HOST_BRIDGE_REGISTER(Register) \
+  PCI_LIB_ADDRESS (                    \
+    HOST_BRIDGE_BUS,                   \
+    HOST_BRIDGE_DEVICE,                \
+    HOST_BRIDGE_FUNCTION,              \
+    Register                           \
+    )
+
+//
+// Host Bridge Device ID (DID) Register
+//
+#define HOST_BRIDGE_DID  HOST_BRIDGE_REGISTER (0x02)
+
+//
+// Host Bridge DID Register values
+//
+#define PCI_DEVICE_ID_INTEL_82441    0x1237  // DID value for PIIX4
+#define PCI_DEVICE_ID_INTEL_Q35_MCH  0x29C0  // DID value for Q35
+
+//
+// Access Power Management PCI Config Regs based on Host Bridge type
+//
+#define PCI_POWER_MANAGEMENT_REGISTER(Register)                  \
+  (PciRead16 (HOST_BRIDGE_DID) == PCI_DEVICE_ID_INTEL_Q35_MCH) ? \
+    Q35_PCI_POWER_MANAGEMENT_REGISTER (Register) :               \
+    PIIX4_PCI_POWER_MANAGEMENT_REGISTER (Register)
+
+//
 // PIIX4 Power Management PCI Configuration Registers
 //
-#define PMBA                PIIX4_PCI_POWER_MANAGEMENT_REGISTER (0x40)
+#define PMBA                PCI_POWER_MANAGEMENT_REGISTER (0x40)
 #define   PMBA_RTE          BIT0
-#define PMREGMISC           PIIX4_PCI_POWER_MANAGEMENT_REGISTER (0x80)
+#define PMREGMISC           PCI_POWER_MANAGEMENT_REGISTER (0x80)
 #define   PMIOSE            BIT0
 
 //
-- 
1.9.3


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