On 11/14/14 15:12, Paolo Bonzini wrote: > > > On 14/11/2014 14:40, Laszlo Ersek wrote: >>>>>> Now where is my thought process wrong? You might want to add an assert >>>>>> somewhere. >>>> >>>> I don't think your thought process is wrong. I think I'm being exactly >>>> as right (or as wrong) as SeaBIOS under all cases, which is what I was >>>> aiming for :) >> Sounds fair enough. > > I think the code is just assuming that the PCI host bridge (bus 0, > device 0, function 0) does not have interrupts. This is the case for > both PIIX4 and Q35.
Yes, I had something like this in mind -- I wasn't smart enough to think of the host bridge, I just figured some internal / reserved device location. Anyway, my request for an ASSERT(blah > 0) comes from there. But, it can be added as a followup (if Gabriel has time for it). Thanks! Laszlo ------------------------------------------------------------------------------ Comprehensive Server Monitoring with Site24x7. Monitor 10 servers for $9/Month. Get alerted through email, SMS, voice calls or mobile push notifications. Take corrective actions from your mobile device. http://pubads.g.doubleclick.net/gampad/clk?id=154624111&iu=/4140/ostg.clktrk _______________________________________________ edk2-devel mailing list edk2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-devel
