Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chen Fan <chen.fan.f...@cn.fujitsu.com>
---
UefiCpuPkg/CpuDxe/CpuMp.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index 71b62be..94b72b7 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.c
+++ b/UefiCpuPkg/CpuDxe/CpuMp.c
@@ -1488,6 +1488,30 @@ ExitBootServicesCallback (
}
/**
+ Specify NMI interruptHandler.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor.This parameter is
processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+**/
+VOID
+EFIAPI
+NMIInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ //
+ // NMI interrupt handler only for wake up AP with hlt state,
+ // so here no routine.
+ //
+ return;
+}
+
+
+/**
Initialize Multi-processor support.
**/
@@ -1497,6 +1521,7 @@ InitializeMpSupport (
)
{
EFI_STATUS Status;
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
gMaxLogicalProcessorNumber = (UINTN) PcdGet32
(PcdCpuMaxLogicalProcessorNumber);
if (gMaxLogicalProcessorNumber < 1) {
@@ -1540,6 +1565,12 @@ InitializeMpSupport (
sizeof (CPU_DATA_BLOCK) *
mMpSystemData.NumberOfProcessors,
mMpSystemData.CpuDatas);
+ /* Register NMI interrupt handler */
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ ASSERT_EFI_ERROR (Status);
+ Status = Cpu->RegisterInterruptHandler (Cpu, 2, NMIInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
mAPsAlreadyInitFinished = TRUE;
Status = gBS->InstallMultipleProtocolInterfaces (
--
1.9.3
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