Folks,
I've been tasked with developing a PEI driver for a PCI device.
So far, I've managed to enumerate bus 0 -- skipping bridge chips for now but
will probably need to support that later -- find the device I'm interested in,
and size the memory BAR's.
My question is this:
Knowing the size I want to map, what's the proper way to
identify/map an area of the PEI memory space to assign to the BAR's? What about
support for I/O vs. MEM space?
What I've found skimming through the EDK2 code looks like only real RAM is
supported. The PEI Spec. doesn't seem to talk about non-physical regions. (DXE
has the MemMapIO type but I don't find any equivalent in PEI.) I hate to wildly
start picking unused address and just start using them. Seems REALLY likely to
break.
Any pointers to information would be appreciated.
Thanks.
-Joe Thomas
// Joseph Thomas
// Principal Software Engineer
// Dot Hill Systems
// 2905 NorthWest Blvd., Suite 20
// Plymouth, MN 55441
// 763.226.2640
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