Load new GDT table and update segment accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff....@intel.com>
CC: Feng Tian <feng.t...@intel.com>
CC: Jiewen Yao <jiewen....@intel.com>
CC: Michael Kinney <michael.d.kin...@intel.com>
---
UefiCpuPkg/CpuMpPei/CpuMpPei.c | 28 ++++++++++++++++++
UefiCpuPkg/CpuMpPei/CpuMpPei.h | 30 +++++++++++++++++++
UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 11 +++++++
UefiCpuPkg/CpuMpPei/Ia32/MpEqu.inc | 24 +++++++++++++++
UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm | 55 +++++++++++++++++++++++++++++++++++
UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.nasm | 49 +++++++++++++++++++++++++++++++
UefiCpuPkg/CpuMpPei/X64/MpEqu.inc | 25 ++++++++++++++++
UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm | 51 ++++++++++++++++++++++++++++++++
UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm | 50 +++++++++++++++++++++++++++++++
9 files changed, 323 insertions(+)
create mode 100644 UefiCpuPkg/CpuMpPei/Ia32/MpEqu.inc
create mode 100644 UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm
create mode 100644 UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.nasm
create mode 100644 UefiCpuPkg/CpuMpPei/X64/MpEqu.inc
create mode 100644 UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm
create mode 100644 UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c
index c1684c2..78299b3 100644
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.c
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.c
@@ -14,6 +14,30 @@
#include "CpuMpPei.h"
+//
+// Global Descriptor Table (GDT)
+//
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {
+/* selector { Global Segment Descriptor } */
+/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
//null descriptor
+/* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}},
//linear data segment descriptor
+/* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}},
//linear code segment descriptor
+/* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}},
//system data segment descriptor
+/* 0x20 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}},
//system code segment descriptor
+/* 0x28 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
//spare segment descriptor
+/* 0x30 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}},
//system data segment descriptor
+/* 0x38 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 1, 0, 1, 0}},
//system code segment descriptor
+/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
//spare segment descriptor
+};
+
+//
+// IA32 Gdt register
+//
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR mGdt = {
+ sizeof (mGdtEntries) - 1,
+ (UINTN) mGdtEntries
+ };
+
/**
The Entry point of the MP CPU PEIM.
@@ -36,6 +60,10 @@ CpuMpPeimInit (
{
+ //
+ // Load new GDT table on BSP
+ //
+ AsmInitializeGdt (&mGdt);
return EFI_SUCCESS;
}
diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
index 00e95cf..611a296 100644
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
@@ -21,6 +21,36 @@
#include <Library/BaseLib.h>
#include <Library/PeimEntryPoint.h>
+#pragma pack(1)
+typedef union {
+ struct {
+ UINT32 LimitLow : 16;
+ UINT32 BaseLow : 16;
+ UINT32 BaseMid : 8;
+ UINT32 Type : 4;
+ UINT32 System : 1;
+ UINT32 Dpl : 2;
+ UINT32 Present : 1;
+ UINT32 LimitHigh : 4;
+ UINT32 Software : 1;
+ UINT32 Reserved : 1;
+ UINT32 DefaultSize : 1;
+ UINT32 Granularity : 1;
+ UINT32 BaseHigh : 8;
+ } Bits;
+ UINT64 Uint64;
+} IA32_GDT;
+#pragma pack()
+/**
+ Assembly code to load GDT table and update segment accordingly.
+
+ @param Gdtr Pointer to GDT descriptor
+**/
+VOID
+EFIAPI
+AsmInitializeGdt (
+ IN IA32_DESCRIPTOR *Gdtr
+ );
#endif
diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf b/UefiCpuPkg/CpuMpPei/CpuMpPei.inf
index 05db141..1dfee4e 100644
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.inf
@@ -31,6 +31,17 @@
CpuMpPei.h
CpuMpPei.c
+[Sources.IA32]
+ Ia32/MpEqu.inc
+ Ia32/MpFuncs.asm | MSFT
+ Ia32/MpFuncs.asm | INTEL
+ Ia32/MpFuncs.nasm | GCC
+
+[Sources.X64]
+ X64/MpEqu.inc
+ X64/MpFuncs.asm | MSFT
+ X64/MpFuncs.asm | INTEL
+ X64/MpFuncs.nasm | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/CpuMpPei/Ia32/MpEqu.inc
b/UefiCpuPkg/CpuMpPei/Ia32/MpEqu.inc
new file mode 100644
index 0000000..2d30db4
--- /dev/null
+++ b/UefiCpuPkg/CpuMpPei/Ia32/MpEqu.inc
@@ -0,0 +1,24 @@
+;------------------------------------------------------------------------------
;
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD
License
+; which accompanies this distribution. The full text of the license may be
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; MpEqu.inc
+;
+; Abstract:
+;
+; This is the equates file for Multiple Processor support
+;
+;-------------------------------------------------------------------------------
+
+PROTECT_MODE_CS equ 10h
+PROTECT_MODE_DS equ 18h
+
+
diff --git a/UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm
b/UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm
new file mode 100644
index 0000000..ca9c15a
--- /dev/null
+++ b/UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm
@@ -0,0 +1,55 @@
+;------------------------------------------------------------------------------
;
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD
License
+; which accompanies this distribution. The full text of the license may be
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; MpFuncs32.asm
+;
+; Abstract:
+;
+; This is the assembly code for MP support
+;
+;-------------------------------------------------------------------------------
+
+.686p
+.model flat
+
+include MpEqu.inc
+.code
+
+
+AsmInitializeGdt PROC near C PUBLIC
+ push ebp
+ mov ebp, esp
+ pushad
+ mov edi, [ebp + 8] ; Load GDT register
+
+ mov ax,cs ; Get the selector data from our code image
+ mov es,ax
+ lgdt FWORD PTR es:[edi] ; and update the GDTR
+
+ push PROTECT_MODE_CS
+ lea eax, SetCodeSelectorFarJump
+ push eax
+ retf
+SetCodeSelectorFarJump:
+ mov ax, PROTECT_MODE_DS ; Update the Base for the new selectors, too
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ popad
+ pop ebp
+ ret
+AsmInitializeGdt ENDP
+
+END
diff --git a/UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.nasm
b/UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.nasm
new file mode 100644
index 0000000..180b637
--- /dev/null
+++ b/UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.nasm
@@ -0,0 +1,49 @@
+;------------------------------------------------------------------------------
;
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD
License
+; which accompanies this distribution. The full text of the license may be
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; MpFuncs.nasm
+;
+; Abstract:
+;
+; This is the assembly code for MP support
+;
+;-------------------------------------------------------------------------------
+
+%include "MpEqu.inc"
+
+SECTION .text
+
+
+global ASM_PFX(AsmInitializeGdt)
+ASM_PFX(AsmInitializeGdt):
+ push ebp
+ mov ebp, esp
+ pushad
+ mov edi, [ebp + 8] ; Load GDT register
+
+ lgdt [edi] ; and update the GDTR
+
+ push PROTECT_MODE_CS
+ mov eax, ASM_PFX(SetCodeSelectorFarJump)
+ push eax
+ retf
+ASM_PFX(SetCodeSelectorFarJump):
+ mov ax, PROTECT_MODE_DS ; Update the Base for the new selectors, too
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ popad
+ pop ebp
+ ret
diff --git a/UefiCpuPkg/CpuMpPei/X64/MpEqu.inc
b/UefiCpuPkg/CpuMpPei/X64/MpEqu.inc
new file mode 100644
index 0000000..f59b2c4
--- /dev/null
+++ b/UefiCpuPkg/CpuMpPei/X64/MpEqu.inc
@@ -0,0 +1,25 @@
+;------------------------------------------------------------------------------
;
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD
License
+; which accompanies this distribution. The full text of the license may be
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; MpEqu.inc
+;
+; Abstract:
+;
+; This is the equates file for Multiple Processor support
+;
+;-------------------------------------------------------------------------------
+
+LONG_MODE_CS equ 38h
+LONG_MODE_DS equ 30h
+
+
+
diff --git a/UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm
b/UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm
new file mode 100644
index 0000000..13a7b5f
--- /dev/null
+++ b/UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm
@@ -0,0 +1,51 @@
+;------------------------------------------------------------------------------
;
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD
License
+; which accompanies this distribution. The full text of the license may be
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; MpFuncs32.asm
+;
+; Abstract:
+;
+; This is the assembly code for MP support
+;
+;-------------------------------------------------------------------------------
+
+include MpEqu.inc
+.code
+
+
+AsmInitializeGdt PROC
+ push rbp
+ mov rbp, rsp
+
+ lgdt fword PTR [rcx] ; update the GDTR
+
+ sub rsp, 0x10
+ lea rax, SetCodeSelectorFarJump
+ mov [rsp], rax
+ mov rdx, LONG_MODE_CS
+ mov [rsp + 4], dx ; get new CS
+ jmp fword ptr [rsp]
+SetCodeSelectorFarJump:
+ add rsp, 0x10
+
+ mov rax, LONG_MODE_DS ; get new DS
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ pop rbp
+ ret
+AsmInitializeGdt ENDP
+
+END
diff --git a/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
b/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
new file mode 100644
index 0000000..bd59572
--- /dev/null
+++ b/UefiCpuPkg/CpuMpPei/X64/MpFuncs.nasm
@@ -0,0 +1,50 @@
+;------------------------------------------------------------------------------
;
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD
License
+; which accompanies this distribution. The full text of the license may be
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; MpFuncs.nasm
+;
+; Abstract:
+;
+; This is the assembly code for MP support
+;
+;-------------------------------------------------------------------------------
+
+%include "MpEqu.inc"
+DEFAULT REL
+SECTION .text
+
+global ASM_PFX(AsmInitializeGdt)
+ASM_PFX(AsmInitializeGdt):
+ push rbp
+ mov rbp, rsp
+
+ lgdt [rcx] ; update the GDTR
+
+ sub rsp, 0x10
+ mov rax, ASM_PFX(SetCodeSelectorFarJump)
+ mov [rsp], rax
+ mov rdx, LONG_MODE_CS
+ mov [rsp + 4], dx ; get new CS
+ jmp far dword [rsp] ; far jump with new CS
+ASM_PFX(SetCodeSelectorFarJump):
+ add rsp, 0x10
+
+ mov rax, LONG_MODE_DS ; get new DS
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ pop rbp
+
+ ret
--
1.9.5.msysgit.0
------------------------------------------------------------------------------
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