Hi Jose, I do not know a good way to do this. A couple of years ago I had some colleges working on thru-wafer-interconnect (TWI) technology as research projects. This is where they used a Bosch Plasma Etcher to "drill" holes clean through the wafer and then connected a series of them in a spiral pattern to form inductors. I suppose one could try this with vias from the top to bottom metal, but you would have to use many, many vias per each 'hole' to keep the series resistance down. Additionally, the depth of each loop would be limited by the top to bottom metal layer separation, orders of magnitude less than a wafer's thickness (~500um).
Since there are inductors in the Electric parts selection for schematics, I imagine someone may know of a good method to lay them out. I would be interested to hear as well, if so. Good luck, Lincoln -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Clockv Sent: Sunday, October 25, 2009 12:52 AM To: Electric VLSI Editor Subject: CMOS INDUCTANCE Hi everyone in the group, I'm having a doubt... Does anyone know how to implement the schematic and layout of an inductor (MOCMOS technology) using electric and ltspice? How can I simulate a RL circuit using above inductor? Can someone send me a *.jelib, so i can see? [email protected] Thanks a lot for any help!!!! --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en -~----------~----~----~----~------~----~------~--~---
