What happens if you place a Power and Ground node in your cell but don't connect them to anything? Jake.
On Thu, Nov 12, 2009 at 11:15 AM, pallav <[email protected]> wrote: > Hi, > > I'm using Electric 8.09 on Mac OS X Snow Leopard running Java: > > java version "1.6.0_15" > Java(TM) SE Runtime Environment (build 1.6.0_15-b03-219) > Java HotSpot(TM) 64-Bit Server VM (build 14.1-b02-90, mixed mode) > > > I think there might be a possible SPICE deck generation bug. Consider > this circuit: http://imagebin.ca/view/hHYxYJgE.html > It is a column multiplexer. However, it does not have any explicit > power/gnd connections. The body for PMOS should be at VDD and at GND > for NMOS. Doing SPICE deck generation gives me this: > > *** WARNING: no power connection for P-transistor wells in cell 'colmux > {sch}' > *** WARNING: no ground connection for N-transistor wells in cell > *'colmux{sch}' > > *** CELL: colmux{sch} > .SUBCKT colmux Asel Asel_b Bsel Bsel_b bit bit0 bit0_b bit1 bit1_b > bit_b > mn...@0 bit0 Asel_b bit N L=0.6U W=2.4U > mn...@1 bit1 Asel bit N L=0.6U W=2.4U > mn...@2 bit0_b Bsel_b bit_b N L=0.6U W=2.4U > mn...@3 bit1_b Bsel bit_b N L=0.6U W=2.4U > mp...@4 bit1 Asel_b bit P L=0.6U W=2.4U > mp...@5 bit0 Asel bit P L=0.6U W=2.4U > mp...@6 bit0_b Bsel bit_b P L=0.6U W=2.4U > mp...@7 bit1_b Bsel_b bit_b P L=0.6U W=2.4U > .ENDS colmux > > > Electric correctly warns about this. However, I am unable to simulate > this circuit in LTSpice using C5_models.txt. LTSpice complains about > not being able to find a suitable model. This is because the body > connection is missing (i.e., the 4th terminal). Something like this > should have been generated: > > mn...@0 bit0 Asel_b bit gnd N L=0.6U W=2.4U > mp...@4 bit1 Asel_b bit vdd P L=0.6U W=2.4U > > This will simulate OK (at-least not give me errors about models not > being found). I wonder if there is an option in Electric that a user > can check to indicate that body connections should be implicit and > Electric generates the 4th terminal connection as well for such > circuits during SPICE deck generation. Maybe it should be turned on by > default. Is this a bug? If so can it be fixed and can a patch be made > available? > > Thanks. > > Kind regards. > > -- > > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<electricvlsi%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=. > > > -- http://CMOSedu.com/jbaker/jbaker.htm -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=.
