Hi Guys, I have followed the Video lecture by Dr, Baker and the other tutorials on his website, they have helped me a lot. I have also share this tool with others and helping them to learn it. I have also provided the info about this tool to the HOD of my Previous College.
I am planning to Layout the design of BGR in electric which i have simulated, its on TSMC 130nm CMOS process and TSMC 180 nm both . Can any body help me with the Technology file of this process. I can edit the technology file for this Process but if some body have this technology then please help me with this . Thanks and Regards. Shashikumar Gautam On Dec 7, 9:20 pm, pallav <[email protected]> wrote: > Your project/scope is too broad. You need to narrow it down before you > can do anything worthwhile. In wireless devices, you could use > Electric for Power Ampflier Design. Investigate various layout > topologies and how they relate to power consumption, heat management, > while meeting design specifications. However, here you will need to > know about RF devices. > > If you are working with mobile devices, you may want to investigate > the ARM core and how to do SoC design (a topic that has been beaten to > death in academia) in a limited power environment. In this scenario, > Electric will be of limited use. > > Maybe a good project for undergrad/MS-level students is using Electric > to implement low power DSP circuits. > > On Dec 7, 12:43 am, Raj Lamsal <[email protected]> wrote: > > > > > Hi, > > greetings, > > i thank you for your valuable suggestion .i am planning to do few topics on > > low power VLSI systems with performance oriented.basically my idea is to > > optimize power and performnce of portable,mobile,wireless devices. > > could you suggest me where should i start from what are the useful tools > > that i can work on, can electric help me doing these,looking forward for > > your valuable suggestions. > > > regards > > RAJ > > > On Sun, Dec 6, 2009 at 9:58 AM, pallav <[email protected]> wrote: > > > > On Dec 4, 11:33 pm, Raj Lamsal <[email protected]> wrote: > > > > can electric be used for low power vlsi design i mean wheather it can > > > > measure the power consumption at the transistor level (circuit level) > > > > It can be used for "low-power" design if you layout the low power > > > circuits. I don't think it can measure power consumption directly as > > > one of the variable it depends upon is switching activity (dependent > > > upon the input vectors). You can however do capacitance extraction. > > > Maybe IRSIM can do dynamic power calculation since its a switch-level > > > simulator. > > > > For large-scale circuits, you are better off estimating power at the > > > RTL/netlist level. Transistor-level will be time-consuming (especially > > > doing logic-simulation to determine switching activity of each gate). > > > > At the cell level, you can do Spice deck generation and use a any > > > Spice simulator to measure power consumption of the cell. Not very > > > practical for big circuits. Depends on your requirements/needs. > > > > -- > > > > You received this message because you are subscribed to the Google Groups > > > "Electric VLSI Editor" group. > > > To post to this group, send email to [email protected]. > > > To unsubscribe from this group, send email to > > > [email protected]<electricvlsi%2bunsubscr...@googlegroups.com> > > > . > > > For more options, visit this group at > > >http://groups.google.com/group/electricvlsi?hl=en. > > > -- > > RRLAMSAL- Hide quoted text - > > - Show quoted text - -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
