Hi Pallav, I have submitted two projects to MOSIS with the same process (C5) you are using. I used the MOCMOS technology for MOSIS in Electric, not SCMOS. Hope that helps.
Lincoln -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of pallav Sent: Thursday, December 10, 2009 12:36 PM To: Electric VLSI Editor Subject: Design fails MOSIS manufacturability review Hi, We are trying to submit a design to MOSIS done on Electric for AMI C5 process (feature size 0.6, lambda 0.35 (http://www.mosis.com/on_semi/ c5/)) using SCMOS rules. I have ran DRC, ERC, NCC checks on the final chip layout and everything passes. We uploaded the design to MOSIS and it failed manufacturability review. The exact errors + requested setup are shown below. Does anybody have any ideas how to fix this in Electric? Since we are using default rules setup in Electric, we haven't changed any sizes (except make metal1/metal2 have widths of 4 as opposed to 3). I'll upload the file incase anyone wants to take a quick look and comment. The zip file will be booth-multiplier.zip. I'll also get in touch with MOSIS to see if they can provide some more information Thanks for any ideas. Project Errors: Undersized CONTACT features (approx 37744) detected Undersized VIA features (approx 8044) detected Undersized VIA2 features (approx 11900) detected Project Warnings: You have authorized MOSIS to add fill to your project to meet minimum layer density requirements. Adding fill could affect the functioning of your design (see http://www.mosis.com/Faqs/faq-design.html#7.0) Project Status: Design 82670 status: FAILED Design name: 8-Bit Booth Multiplier Technology: SCN3M, lambda = .35 Fabrication restricted to AMI only. Fill to be added: by MOSIS This project can be fabricated on a AMI_C5F run. POLY layer drawn density (1.6%) plus estimated fill (10.8%) meets the AMI_C5F minimum required (12.0%). METAL1 layer drawn density (6.0%) plus estimated fill (27.0%) meets the AMI_C5F minimum required (30.0%). Run date requested: 18-JAN-2010 Layout format: GDS Top or root structure is "chip". Layout file: complete; Binary CRC checksum: 2294847872, 643072 Intended disposition: RESEARCH Bonding pads: 40 Layout size: 1467 x 1467 microns; area: 2.152 sq millimeters Layers found (and densities): CONTACT, P_WELL, N_WELL, ACTIVE, P_PLUS_SELECT, N_PLUS_SELECT, POLY (1.6%), METAL1 (6.0%), VIA, METAL2 (36.7%), GLASS, VIA2, METAL3 Requested quantity: 5 Requested packaging: DIP40 [MOSIS generated bonding diagram] (5 parts) Maximum die size: 7620 x 7620 -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
