On Nov 17, 9:50 pm, John <[email protected]> wrote: > sorry to double post, I noticed Alexandre Rusev mentioned using Orcad Yes ORcad tools a wrorking for Xilinx. yet I mainly use Xilinx Platfrom studio, and some times Quartus for Altera chips. > Express to do the synthesis. Is that true? Orcad can take an electric > Schematic and make it into a Xilinx Coolrunner II implementation? It > sounds farfetched, but I just want to make sure
Altera Quartus Webpack is not much simpler ... >Are all the vendor programs really equally bad? Is there any one of >them that is even remotely reliable? I afraid that situation is really near that.;) Yet using Xilinx tools 11.1 (WebPack 11.1) is also available I create even embededd processor and custom peripherials quite successfully. Simple projects likes VGA signal generator typically create no trouble with WebPack 11.1. Don't you think about switching to HDL based design from the schematic design? For simulation of HDL you can use GHDL,GEDA, IcarusVerilog e.t..c. >I was talking about the second scenario, unfortunately. I suppose the >best I can do with Electric is draw it in that program to make sure my >circuit works, then copy the design into Xilinx ISE so I know that >it's Xilinx's fault if it doesn't work, and not my design. So do I understand correctly that you have your design compiled successfully, yet it doesn't work as expected? If so, first of all please do gate level simulation with simulator supplied with Xilinx tools. Whay don't you use it? Is something likes ModelSim is included into your WebPack 10.x? You can use any free or commercial simulator for example KSimus or Electric+IRSIM or whatever you like. I guess the only you need is ability to exchange your schematic files between Xilinx tools and the tools where you draw and/or simulate your schematics. Electric IRSIM is quite useful for simulating. Intheory you can try to carry out your task with Electric! It's quite likely that finally you see the design is working fine in simulator, but fails in hardware. If so, then you have to investigate it on respect to external asynchronous signals, "gated clock" constructions in your schematics, time jitters and races. Don't be afraid, FPGA/CPLD projects are typically don't work ate the beginning!;) And projects with Altera chips too... One more alternative you can use is instrumental debugging. If you have 4 channel oscilloscope (Tektronix 2024a for example, it has relatively low cost and nice functionality for it's class of instruments). Route your signals out from your chip and verify that all signals are stabilsed before clock edge arriving. Often it's convinient to low the chip clocking frequency downto 1-5MHz due to avoid distrotions caused by oscilloscope probes and avoid need of calibrating/tunning the probes. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
