Hi All, I have a schematic that includes bus exports. I would like to extract the verilog code and run verilog simulations. I noticed that when I extract the verilog code from Tools --> Simulations(Verilog) -> Write Verilog Deck, the bus index format is not preserved. For example:
the schematic has an export in[1:32][A][new,old], when electric writes the verilog deck, the ports are now type reg but 1-bit like in_1_A_new, in_1_A_old, etc. I am wondering if there is a way that I can make the verilog code to say reg [1:32] in_A_new, in_A_old etc. And I tried checking the verilog preferences for "preserve verilog formatting" and "parameterize verilog module names", its still the same. I appreciate any help or suggestions. Thanks -Nav -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
