Also how should we realize external capacitance in electric?? As we realised resistance using n-wells(in tutorial 1)...
On Mar 6, 9:41 pm, Nikhil Kumar Das <[email protected]> wrote: > I made a layout of a simple transconductor(OTA) in Electric. > After simulating the netlist from layout I observed that no parasitic > capacitances were extracted(I checked the settings in > Preferences->Tools->Parasitic). What to do? > > Also after simulating the netlist obtained I got a totally different > AC response for the OTA(normally its a low-pass-single pole system.) > In many places the drain and source were interchanged as desired(what > is the technique for getting desired drain/source?). Also after > editing the netlist to get same drain source combinations still the > response was way different than desired. Will the nmos/pmos locations > matter (like placing an nmos above or below a pmos) in the final > netlist and the response?? > > Kindly help! -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
