Hi, I looks like you have violated a design rule size error and it is telling you that the rule is 12 and you are at 11. When you have run the DRC, use the > key to cycle through the errors and the parts that are too close will be highlighted, select select the part that is too thin and select its properties and change the width to 12. Errors usually come in multiples so if you fix this first error, the second error will probably fix.
DRC is the "design rule checker" and the error message is quite descriptive telling you what the rule is that is violated, what node is at fault, and even what exactly is the problem (less than 12 wide) and what you have (is 11). ~Chris On May 3, 9:18 am, Yugal <[email protected]> wrote: > Hi, > I have been wondering for the solution to this error. > ayout DRC (full) error 1 of 2: Minimum width/height error((X axis)): > cell 'completed_2to1_mux_layout{lay}' node Metal-1-N-Well- > Con['well@0'], layer 'N-Well' LESS THAN 12 WIDE (IS 11) [rule '1.1 > Mosis, SUBM'] > Please help me. There's no other DRC error, no LVC or NCC errors and > no ECC errors. > I can't understand it. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
