Hi Yugal, Send me your library file. Also send me the errors you are concerned about and your settings such as technology selected, metal layers, technology node setting etc.
On Tuesday, May 1, 2012 8:46:06 AM UTC-4, Yugal wrote: > > I am a rookie.I am working on a project, its layout design of 4:1 > Multiplexer. > I have planned to make it using three 2:1multiplexers. I made a cell > for 2:1 mux in electric vlsi 9.01 > There's no DRC error. I did "compaction" (there's an option in > electric). But there's ERC well check error as well as are coverage > error. Why's that? > I can send you the library file so that you can suggest me something. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To view this discussion on the web visit https://groups.google.com/d/msg/electricvlsi/-/52hdOjae3QkJ. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
