try to decrease reltol and see
On Mon, Jul 29, 2013 at 6:02 PM, Usama Awais <[email protected]>wrote: > Hi there, > Assalamoalaikum! > > I used electric with LT SPICE to make a 6-bit ADC. I am facing problems in > the resistive ladder network. When I simulate the voltages for each > reference to the input of a comparator, instead of giving an expected > linear voltage level, it gives a very noisy non linear behavior (Attached > snapshot). The waveform indicate the references of the top 2 comparators > (63rd and 62nd). I have also attached digrams for my schematics. When I > used this configuration for a 3 bit ADC, the reference voltages entering > the comparators are perfectly linear (however not in this case of a 6 bit > ADC). What could be the reason for this and any suggestions to correct it > > Regards > Usama Awais > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/groups/opt_out. > > > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
