In short, it seems you must have a complete (or more than it was originally) circuit.
You can use a cell to make the layout. This can be seen in the attached jelib. On Mon, Nov 11, 2013 at 5:01 PM, R. Jacob Baker <[email protected]>wrote: > The MOSFET is a four terminal device. When you use the three terminal pMOS > node Electric connects the well to vdd, but you have the vdd symbol in the > cell. The schematic you sent won't connect the bodies anywhere. Further the > bodies (n-well) of your p Transistor layouts are not connected. It doesn't > make sense to NCC these incomplete drawings. > > To see what Electric is doing with no body connections I generated the > spice netlist for the schematic resulting in: > > MM1 M1_d M1_g net@0 PMOS L=1.2U W=24U > MM2 net@0 M2_g M2_s PMOS L=1.2U W=24U > > As expected no body connection (the syntax is: Mname D G S *B* model name > L= W=), B is missing above. > > Next I generated the spice netlist from the layout: > > MM1 net@0 M1_poly-left net@1 *vdd* PMOS L=1.2U W=24U AS=39.6P AD=39.6P > PS=51.3U > +PD=51.3U > MM2 net@2 M2_poly-left net@0 *vdd* PMOS L=1.2U W=24U AS=39.6P AD=39.6P > PS=51.3U > +PD=51.3U > > Even though there isn't a well connection the bodies are tied to vdd > (perhaps this is a bug...though the well check would catch it). > > Can you post some examples of the problem with correct body connections in > both schematics and layouts along with complete circuits? Perhaps there is > an issue (hash code) but all of these other problems are hiding it. > > > On Mon, Nov 11, 2013 at 3:23 PM, Alexander Bradley < > [email protected]> wrote: > >> I created an entire new library and remade the circuit. >> >> I have tested this using the pre-defined nodes. >> >> This problem still occurs randomly when I LVS. >> >> >> On Mon, Nov 11, 2013 at 7:18 AM, R. Jacob Baker <[email protected]>wrote: >> >>> In the "error{lay}" cell you are using a cell called PMOS_W80_L4 and in >>> the "error{sch}" cell you are using pMOS nodes. >>> >>> A cell won't NCC to a node even though they may be functionally the >>> same. >>> >>> >>> On Sun, Nov 10, 2013 at 11:29 PM, Alexander Bradley < >>> [email protected]> wrote: >>> >>>> >>>> >>>> >>>> On Sun, Nov 10, 2013 at 3:17 PM, Travis Ayres <[email protected]>wrote: >>>> >>>>> Can you attach your files? >>>>> On Nov 10, 2013 3:13 PM, <[email protected]> wrote: >>>>> >>>>>> The error, Parts (hash code), can be seen in the attached image. >>>>>> >>>>>> The circuit is quite simple and I hope my mistake is simple as well. >>>>>> >>>>>> The error occurs when I LVS. It does *not* occur everytime I LVS, >>>>>> however. >>>>>> >>>>>> Any solutions/guesses? >>>>>> >>>>>> -- >>>>>> You received this message because you are subscribed to the Google >>>>>> Groups "Electric VLSI Editor" group. >>>>>> To unsubscribe from this group and stop receiving emails from it, >>>>>> send an email to [email protected]. >>>>>> For more options, visit https://groups.google.com/groups/opt_out. >>>>>> >>>>> -- >>>>> You received this message because you are subscribed to the Google >>>>> Groups "Electric VLSI Editor" group. >>>>> To unsubscribe from this group and stop receiving emails from it, send >>>>> an email to [email protected]. >>>>> For more options, visit https://groups.google.com/groups/opt_out. >>>>> >>>> >>>> -- >>>> You received this message because you are subscribed to the Google >>>> Groups "Electric VLSI Editor" group. >>>> To unsubscribe from this group and stop receiving emails from it, send >>>> an email to [email protected]. >>>> For more options, visit https://groups.google.com/groups/opt_out. >>>> >>> >>> >>> >>> -- >>> http://cmosedu.com/jbaker/jbaker.htm >>> >>> -- >>> You received this message because you are subscribed to the Google >>> Groups "Electric VLSI Editor" group. >>> To unsubscribe from this group and stop receiving emails from it, send >>> an email to [email protected]. >>> For more options, visit https://groups.google.com/groups/opt_out. >>> >> >> -- >> You received this message because you are subscribed to the Google Groups >> "Electric VLSI Editor" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to [email protected]. >> For more options, visit https://groups.google.com/groups/opt_out. >> > > > > -- > http://cmosedu.com/jbaker/jbaker.htm > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/groups/opt_out. > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
test2.jelib
Description: Binary data
