Hi All, I found the following in the manual, Ch. 9 NCC section. I actually knew this and had forgotten ;-)
I made s short video, http://cmosedu.com/videos/electric/PMOS_Body/PMOS_Body.html , to show how it works. Note that you only have to be concerned with this if your PMOS body isn't tied to vdd. <https://lh5.googleusercontent.com/-W3Z52p_0j70/UpAaSVz_bJI/AAAAAAAAAPA/gIDivJhZiiw/s1600/Capture.JPG> On Thursday, November 21, 2013 6:14:52 PM UTC-8, rjacobbaker wrote: > > Hi All, > > Attached is the jelib of a simple PMOS divider. In both the layout and the > schematic the body and source are tied together. For the schematic we get > the correct (meaning S and B are connected), SPICE netlist, > > Mpmos-4@0 net@4 net@4 vdd vdd PMOS L=1.8U W=1.8U > Mpmos-4@1 Vo_3 Vo_3 net@4 net@4 PMOS L=1.8U W=1.8U > Mpmos-4@2 gnd gnd Vo_3 Vo_3 PMOS L=1.8U W=1.8U > > However, for the layout we get the incorrect > > Mpmos@0 net@0 net@0 vdd vdd PMOS L=1.8U W=1.8U > Mpmos@1 Vo_3 Vo_3 net@0 vdd PMOS L=1.8U W=1.8U > Mpmos@2 gnd gnd Vo_3 vdd PMOS L=1.8U W=1.8U > > where the body of the PMOS is tied to vdd even though it isn't! > > The cells don't NCC if the following is checked even though they should. > > [image: Inline image 1] > > Also, you have to de-select that the n-well must connect to power in the > well checks: > > [image: Inline image 2] > > Hopefully, the solution to this is selecting a different layout node for > the PMOS device; however, I have tried this and it doesn't work. > > Thanks in advance for shedding some light on this, Jake. > > -- > http://cmosedu.com/jbaker/jbaker.htm<http://www.google.com/url?q=http%3A%2F%2Fcmosedu.com%2Fjbaker%2Fjbaker.htm&sa=D&sntz=1&usg=AFQjCNE3204wIdEGoUKDxxfJ0jSSGbpNCQ> > > > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
