Hi everyone, The title says my question, or more simply put: has anyone implemented a foundry provided PDK for deep submicron process such as 45nm or below in the Electric VLSI CAD for any real chip design project? As is known that the scaler mos technology from MOSIS accompanied by Electric CAD can't be used for deep submicron design, we have to use foundry specific PDKs for 45nm or below. However, PDKs provided by mainstream foundries are always created for leading EDA tools like those from Cadence, etc., I find it's a daunting job trying to actually implement those design rules provided by foundries since for a deep submicron process like 45nm, there're seemingly more design rules in 45nm or below process than Technology Creation Wizard in Electric can take care, as I've been reading through foundry provided nearly 600-page document for design rules. Is it a much simpler and easier way for me to just resort to a physical IP provider such as ARM and import its foundry specific cell library sets for a particular deep submicron process - I assume these library sets have already been designed with foundry's design rules?
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