I was able to do the parasitic extraction from the Layout of the inverter.
When I simulated the extracted file, its response is coming same as
schematic simulation. I feel this is incorrect. Can anybody tell me, where
I am making the extraction. I have attached the schematic and extracted
file along with this.
*Extracted Spice File from the layout: *
*** TOP LEVEL CELL: EE307W09:InvLoad{lay}
Mnmos@0 gnd In#1nmos@0_poly-left Out nmos@0_n-trans-well NMOS L=0.6U W=1.2U
+AS=3.24P AD=5.22P PS=7.65U PD=13.2U
Mpmos@0 Out In#2pmos@0_poly-right vdd pmos@0_p-trans-well PMOS L=0.6U
W=1.2U
+AS=6.39P AD=3.24P PS=16.2U PD=7.65U
** Extracted Parasitic Capacitors ***
C0 Out 0 6.18fF
C1 In 0 1.753fF
C2 In#1nmos@0_poly-left 0 0.157fF
C3 In#2pmos@0_poly-right 0 0.162fF
** Extracted Parasitic Resistors ***
R0 In#1nmos@0_poly-left In#1nmos@0_poly-left##0 9.3
C4 In#1nmos@0_poly-left##0 0 0.157fF
R1 In#1nmos@0_poly-left##0 In#1nmos@0_poly-left##1 9.3
C5 In#1nmos@0_poly-left##1 0 0.157fF
R2 In#1nmos@0_poly-left##1 In#1nmos@0_poly-left##2 9.3
C6 In#1nmos@0_poly-left##2 0 0.157fF
R3 In#1nmos@0_poly-left##2 In#1nmos@0_poly-left##3 9.3
C7 In#1nmos@0_poly-left##3 0 0.157fF
R4 In#1nmos@0_poly-left##3 In 9.3
R5 In In##0 9.3
C8 In##0 0 0.162fF
R6 In##0 In##1 9.3
C9 In##1 0 0.162fF
R7 In##1 In##2 9.3
C10 In##2 0 0.162fF
R8 In##2 In##3 9.3
C11 In##3 0 0.162fF
R9 In##3 In##4 9.3
C12 In##4 0 0.162fF
R10 In##4 In#2pmos@0_poly-right 9.3
* Spice Code nodes in cell cell 'EE307W09:InvLoad{lay}'
vdd vdd 0 DC 3
vin Vin 0 PULSE(0 3 0 1pS 1pS 5mS 10mS)
.tran 0 30ms
.include /home/user/.wine/drive_c/Program Files/LTC/LTspiceIV/C5_models.txt
.END
*Schematic Spice File*
.SUBCKT cmos_inv Vin Vout
** GLOBAL gnd
** GLOBAL vdd
Mnmos@2 Vout Vin gnd gnd NMOS L=0.6U W=3U
Mpmos@2 vdd Vin Vout vdd PMOS L=0.6U W=6U
.ENDS cmos_inv
.global gnd vdd
*** TOP LEVEL CELL: I1{sch}
Xcmos_inv@0 cmos_inv@0_Vin cmos_inv@0_Vout cmos_inv
* Spice Code nodes in cell cell 'I1{sch}'
vdd vdd 0 DC 3
vin Vin 0 DC 0
.dc Vin 0 5 1m
.include /home/user/.wine/drive_c/Program Files/LTC/LTspiceIV/C5_models.txt
.END
Can anybody help me on this?
--
Soorya Krishna K
Department of Electronics and Communication Engineering
Srinivas Institute of Technology, Valachil, Mangalore - 574143
Email : [email protected]
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