The Website of Berkeley's PTM project is http://ptm.asu.edu/latest.html.
Am Freitag, 14. November 2014 09:46:04 UTC+1 schrieb Jack Jost: > > If you want to do "generic prototyping", before targeting a particular > foundry process, you might be interested in the "Predictive Technology > Model" spice parameter sets. The publication list contains graphs showing > how well these matched to actual process nodes in the past. Based on a > design using these generic models it should be straightforward to do the > fine-tuning for a particular foundry as soon you get the real PDK, either > manually for your cell library, or possibly even using one of the automatic > sizing tools. > > - J > > > Am Mittwoch, 12. November 2014 15:47:46 UTC+1 schrieb parrotmarc: >> >> Hello, >> >> Can Electric VLSI be used to simulate a handmade 28nm layout? >> Does MOSIS or someone else provide free spice parameters to do it? >> >> Best regards, >> Marc. >> >> -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
