Hi, I noticed when creating an nMOS transistor, Electric will create the spice deck differently for the schematic compared to the layout. Don't have this problem with pMOS. See below, drain source are backwards for the spice deck of the layout. Anyone know why or how to correct this?
Many thanks... <https://lh5.googleusercontent.com/-EsZOSZuCZFs/VGmoTQa6z2I/AAAAAAAAAQ0/Cpb63HrtBrE/s1600/2014-11-17_10-33-09.jpg> -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
