I have the same problem. I just mirror the nMOS and then it is ok. Seems there is some preference for source and drain; it is pre-determined, and this is not what I expected. Maybe it's too hard to determine source and drain automatically. You can see the effect when the SPICE deck is created. In Electric, it seems the source and drain depend on physical orientation of your nmos- probably same for PMOS. I'll give that at try...
I questioned this last year in this forum but i don't think there was any reply.. On Saturday, October 24, 2015 at 5:19:02 PM UTC+3, tltoth wrote: > > Hi, > > I placed an NMOS transistor layout and exported its pins. > The spice deck generation ended up with swapped s and d pins. > Is there a rule to follow during the naming to get what is expected? > How does the spice deck generation work? > > Thanks > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
