This error occurs when no metal is selected.
You see under preferences -> Tools-> Silicon compiler that no layer is
selected for horizontal and vertical lines,
Go to a layout cell select a M1 line. Go back to the VHDL cell and start
silicon compiler.
Am Donnerstag, 22. Oktober 2015 17:23:30 UTC+2 schrieb Michael Chen:
>
> Hi all,
>
> I'm trying to use the silicon compiler on the samples library file and I'm
> getting this error:
>
> Reading Standard Cell Library 'sclib'
> Compiling VHDL in cell 'tool-SiliconCompiler{vhdl}' ... Done, created cell
> 'tool-SiliconCompiler{net.quisc}'
> Reading netlist in cell 'tool-SiliconCompiler{net.quisc}'
> Placing cells
> Routing cells
> Generating layout
> SC Maker cannot find Horizontal Arc Solid in technology mocmos
>
> I saw the topic here
> <https://lists.gnu.org/archive/html/discuss-gnu-electric/2011-03/msg00001.html>
> but
> I already have mocmos set to startup tech and layout tech under Defaults.
>
> I am trying to eventually use my own technology library but I ran into
> this error when trying to convert my VHDL using the silicon compiler, what
> does this error mean?
>
> Thanks!
> -Mike
>
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