Hey Gavin, <https://lh3.googleusercontent.com/-fykTswsErEQ/WgqPY9DRuKI/AAAAAAAAChE/uAmFQw6hHv4LFx7xnqZ1zb8utYTNZCCjgCLcBGAs/s1600/drc.png>
<https://lh3.googleusercontent.com/-dAA4vo0umIg/WgqPcw27oUI/AAAAAAAAChI/4iQyB0zcEnoLZqGNu7fieHIooM9Fm3-XgCLcBGAs/s1600/layout.png> Could you please help me with a step by step tutorial of generating layout of NCNFET and PCNFET transistor as in DRC I am getting warning as "no layer 'N-Active-Well' in mocmos-cn". I attach the layout of a simple inverter and DRC run message. On Friday, November 10, 2017 at 9:11:13 PM UTC+5:30, Gavin wrote: > > > > Currenlty Iam working on cnfet. So. using electriv 9.07. I have a > > problem with DRC run.. > > Everytime I am running DRC...its giving error as" > > ArrayIndexOutOfBound: Exception 0 > > Placing just the NCN-Transistor in a layout and doing the DRC, I see the > same thing (as seen in the attached "CNFET DRC.jpg"). The odd thing is > that the same error doesn't seem to happen if Multi-threaded DRC [1] is > turned on. Which makes me think, that it might be caused by an Electric > 9.07 or JAVA 1.8.0_152 bug for single threaded DRC. > > > Also I dont find schematic pallete for CNFET. > > Please guide me through it. May be I am not able to do installation > > correctly. > > If it is the nCNFET and pCNFET of Fig. 1(a) and Fig. 1(b) of the article > titled "A CAD tool for design and analysis of CNFET circuits" [2] that > you are looking for. > > It looks like those might be the nMOS CN and pMOS CN that you get when > you click on the black arrow in the bottom right corner of transistor > component for the schematic (as seen in the attached "CN schematics.jpg"). > > [1] http://www.staticfreesoft.com/jmanual/mchap09-02-02.html > [2] https://doi.org/10.1109/EDSSC.2010.5713735 > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
