Dear Electric Group: We can propose to electric users to work together and collaborate to create a SoC for the 180 nm.
Google plans s free shuttle tape put for interested chip makers to use the process for both analog and digital design, what is good from this process is they have already thr digital logic cells. A collaboration for analog design engineers to use electric to make the analog cells with one goal. Both 32/64 bit Core can be used as efabless Tim Edwards mention in some workshop. I can both participate in doing analog design and layout. Best Regards, Joselito On Mon, Sep 14, 2020, 11:07 AM Abel Joseph John <[email protected]> wrote: > > Will Electric add support for the to be released SkyWater PDK? > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To view this discussion on the web visit > https://groups.google.com/d/msgid/electricvlsi/8d6feba0-e425-47ff-a0b9-4acf8ab0a3b1n%40googlegroups.com > <https://groups.google.com/d/msgid/electricvlsi/8d6feba0-e425-47ff-a0b9-4acf8ab0a3b1n%40googlegroups.com?utm_medium=email&utm_source=footer> > . > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/CALy8%2BG7B-REhG2dRsLYiGbDd_GDq265VVT1v7TJp9Ry9dFFCkg%40mail.gmail.com.
