With SkyWater PDK 130nm we have: - a number of special layers which mark various type of capacitors, resistors, inductors etc. Various oxide thickness markers likes high voltage are also used - instead of lowes metal layer they are using that bloody local interconnect layer "li" (I guess it must be hight resistive wolfram)
So I have questions how to describe several thing in Electric tech file?: - how to describe that via4 connects metal5 to cap2m if one (cap2m) present and to metal4 otherwise? - how to describe that when metal1 is connected to active/diffusion the connection is NOT m1-to-active-contact, but that "sandwich" of *mcon*+*li*+*licon*, but *licon* is also independent "pseudometal" layer which is connected to active with licon? - does Electric already have some facility for generating inferred layers in GDS output? I mean writing *mcon*+*li*+*licon* instead m1-to-active-contact when writing GDS Steven, could you give an advice on issues above, looking on their layers map, please??? I also tried to ask the same question description of LIL for other technology, this time I tied to provide more clear formulation https://skywater-pdk.readthedocs.io/en/latest/rules/assumptions.html https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html#device-and-layout-vs-schematic [image: SkyWater SKY130 Process Stack] -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/CACoSTq%2BXNy5F6%2BTpFZqaZFS7sRAQdMJXccsGtjDwcCPhFwHD-g%40mail.gmail.com.
