Hi , When i tried manually bring the transistors closer, it is resulting in DRC, however when i tried it using the compact option it is not leading to DRC problem the optimal area as per expectation. Same problem is seen even when i integrate 2 block level layout designs. If i try manually, tool says drc problem and it wont allow to bring the block levels closer (This always leaves a gap between the block level design in the top level), but when i do the compaction it is able to get it with the minimum area. What could be the reason why tool is erroring out when the modules are moved closer manually, and how is compact helping this. Is this a bug in electric by any chance or I'm i missing something.
I can share snapshots if required. Regards, Bibin -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/0227304e-8fca-4a8b-9c59-cf0639977da5n%40googlegroups.com.
