>They certainly don't recognize resistive poly layers. Okay, I'll think on approach to add this feature. I need to understand algos of resistor parasitic capacitance extractions, used by other tools... Is the technology->factors->Minimum Resistane the value presumed to be used for splitting resistors into "lumped resistor elements" before inserting parasitic capacitors to ground?
On Thu, Jun 17, 2021 at 9:30 AM <[email protected]> wrote: > [email protected] > <https://groups.google.com/forum/?utm_source=digest&utm_medium=email#!forum/electricvlsi/topics> > Google > Groups > <https://groups.google.com/forum/?utm_source=digest&utm_medium=email/#!overview> > <https://groups.google.com/forum/?utm_source=digest&utm_medium=email/#!overview> > Topic digest > View all topics > <https://groups.google.com/forum/?utm_source=digest&utm_medium=email#!forum/electricvlsi/topics> > > - Do we have parasitic capacitance extraction for resistors? > <#m_7149361369837820236_group_thread_0> - 2 Updates > - electric not allowing to bring block level cells closer in top level > <#m_7149361369837820236_group_thread_1> - 1 Update > > Do we have parasitic capacitance extraction for resistors? > <http://groups.google.com/group/electricvlsi/t/efe7d1afe7abc739?utm_source=digest&utm_medium=email> > Alexandre Rusev <[email protected]>: Jun 16 10:23PM +0300 > > Do we have parasitic capacitance extraction for resistors? > > Thought technology defend parasitic capacitance for resistive poly layer I > don't see parasitic capacitance lumped elements for reistors in spice > netlist. > > Am I doing something wrong or this feature is not supported now? > > > The reason why I need them is following: > We are working on multiphase ring oscillators with resistive feedbacks. > These oscillators are used for building picotimers so they are running at > critical speeds (likes 2.5GHz for 180nm process), so post layout simulation > which takes into account resistors parasitics caps is very important for > us. > Steven Rubin <[email protected]>: Jun 16 12:35PM -0700 > > Support for parasitics in the Spice decks is weak. There are a two > options in the "Spice/CDL" Preferences: "Trans area/perimeter only" and > "Conservative RC". Neither is as good as you probably want, and they may > not work on resistors at all. They certainly don't recognize resistive > poly layers. > > -Steven Rubin > > On 6/16/2021 12:23 PM, Alexandre Rusev wrote: > Back to top <#m_7149361369837820236_digest_top> > electric not allowing to bring block level cells closer in top level > <http://groups.google.com/group/electricvlsi/t/af1869d0a878ae58?utm_source=digest&utm_medium=email> > student_learner <[email protected]>: Jun 16 03:14AM -0700 > > Hi , > > When i tried manually bring the transistors closer, it is resulting in > DRC, > however when i tried it using the compact option it is not leading to DRC > problem the optimal area as per expectation. Same problem is seen even > when i integrate 2 block level layout designs. If i try manually, tool > says > drc problem and it wont allow to bring the block levels closer (This > always > leaves a gap between the block level design in the top level), but when i > do the compaction it is able to get it with the minimum area. What could > be the reason why tool is erroring out when the modules are moved closer > manually, and how is compact helping this. Is this a bug in electric by > any > chance or I'm i missing something. > > I can share snapshots if required. > > Regards, > Bibin > Back to top <#m_7149361369837820236_digest_top> > You received this digest because you're subscribed to updates for this > group. You can change your settings on the group membership page > <https://groups.google.com/forum/?utm_source=digest&utm_medium=email#!forum/electricvlsi/join> > . > To unsubscribe from this group and stop receiving emails from it send an > email to [email protected]. > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/CACoSTq%2BWom55oZknEOQg1m3y70cDGKwHU0psw720OxvN8NcwCw%40mail.gmail.com.
