* libelf/elf.h: Add NT_RISCV_USER_CFI, add NT and EF comments
for s390-32 only flags. Update RISC-V relocations. Add
NT_ARM_GCS and NT_RISCV_TAGGED_ADDR_CTRL. Remove ILP32 AArch64
relocs. Define GNU_PROPERTY_AARCH64_FEATURE_1_GCS. Add
NT_X86_XSAVE_LAYOUT and NT_ARM_POE.
Signed-off-by: Mark Wielaard <[email protected]>
---
libelf/elf.h | 48 ++++++++++++++++++++++--------------------------
1 file changed, 22 insertions(+), 26 deletions(-)
None of the new (or removed) constants are used in the code yet.
This is just to make sure the next glibc sync isn't even bigger.
diff --git a/libelf/elf.h b/libelf/elf.h
index 33aea7f743b8..b482fcfb6489 100644
--- a/libelf/elf.h
+++ b/libelf/elf.h
@@ -1,5 +1,5 @@
/* This file defines standard ELF types, structures, and macros.
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2026 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -797,7 +797,9 @@ typedef struct
#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */
#define NT_X86_SHSTK 0x204 /* x86 SHSTK state */
-#define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */
+#define NT_X86_XSAVE_LAYOUT 0x205 /* XSAVE layout description. */
+#define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves. This was
+ used in now removed s390-32 arch. */
#define NT_S390_TIMER 0x301 /* s390 timer register */
#define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */
#define NT_S390_TODPREG 0x303 /* s390 TOD programmable
register */
@@ -835,12 +837,17 @@ typedef struct
#define NT_ARM_ZA 0x40c /* ARM SME ZA registers. */
#define NT_ARM_ZT 0x40d /* ARM SME ZT registers. */
#define NT_ARM_FPMR 0x40e /* ARM floating point mode register. */
+#define NT_ARM_POE 0x40f /* ARM POE registers. */
+#define NT_ARM_GCS 0x410 /* ARM GCS state. */
#define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note. */
#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers. */
#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode. */
#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers. */
#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers
*/
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
+#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged
+ address control */
+#define NT_RISCV_USER_CFI 0x903 /* RISC-V shadow stack state */
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers. */
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and
status registers. */
@@ -919,7 +926,7 @@ typedef struct
#define DT_SYMTAB_SHNDX 34 /* Address of SYMTAB_SHNDX
section */
#define DT_RELRSZ 35 /* Total size of RELR relative
relocations */
#define DT_RELR 36 /* Address of RELR relative
relocations */
-#define DT_RELRENT 37 /* Size of one RELR relative
relocaction */
+#define DT_RELRENT 37 /* Size of one RELR relative relocation
*/
#define DT_NUM 38 /* Number used */
#define DT_LOOS 0x6000000d /* Start of OS-specific */
#define DT_HIOS 0x6ffff000 /* End of OS-specific */
@@ -1389,6 +1396,7 @@ typedef struct
#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
+#define GNU_PROPERTY_AARCH64_FEATURE_1_GCS (1U << 2)
/* The x86 instruction sets indicated by the corresponding bits are
used in program. Their support in the hardware is optional. */
@@ -2903,19 +2911,6 @@ enum
#define R_AARCH64_NONE 0 /* No relocation. */
-/* ILP32 AArch64 relocs. */
-#define R_AARCH64_P32_ABS32 1 /* Direct 32 bit. */
-#define R_AARCH64_P32_COPY 180 /* Copy symbol at runtime. */
-#define R_AARCH64_P32_GLOB_DAT 181 /* Create GOT entry. */
-#define R_AARCH64_P32_JUMP_SLOT 182 /* Create PLT entry. */
-#define R_AARCH64_P32_RELATIVE 183 /* Adjust by program base. */
-#define R_AARCH64_P32_TLS_DTPMOD 184 /* Module number, 32 bit. */
-#define R_AARCH64_P32_TLS_DTPREL 185 /* Module-relative offset, 32
bit. */
-#define R_AARCH64_P32_TLS_TPREL 186 /* TP-relative offset,
32 bit. */
-#define R_AARCH64_P32_TLSDESC 187 /* TLS Descriptor. */
-#define R_AARCH64_P32_IRELATIVE 188 /* STT_GNU_IFUNC
relocation. */
-
-/* LP64 AArch64 relocs. */
#define R_AARCH64_ABS64 257 /* Direct 64 bit. */
#define R_AARCH64_ABS32 258 /* Direct 32 bit. */
#define R_AARCH64_ABS16 259 /* Direct 16-bit. */
@@ -3477,7 +3472,9 @@ enum
/* Valid values for the e_flags field. */
-#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed.
*/
+#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed.
+ This was used in now removed s390-32
+ arch. */
/* Additional s390 relocs */
@@ -4088,6 +4085,7 @@ enum
#define R_RISCV_TLS_DTPREL64 9
#define R_RISCV_TLS_TPREL32 10
#define R_RISCV_TLS_TPREL64 11
+#define R_RISCV_TLSDESC 12
#define R_RISCV_BRANCH 16
#define R_RISCV_JAL 17
#define R_RISCV_CALL 18
@@ -4113,16 +4111,10 @@ enum
#define R_RISCV_SUB16 38
#define R_RISCV_SUB32 39
#define R_RISCV_SUB64 40
-#define R_RISCV_GNU_VTINHERIT 41
-#define R_RISCV_GNU_VTENTRY 42
+#define R_RISCV_GOT32_PCREL 41
#define R_RISCV_ALIGN 43
#define R_RISCV_RVC_BRANCH 44
#define R_RISCV_RVC_JUMP 45
-#define R_RISCV_RVC_LUI 46
-#define R_RISCV_GPREL_I 47
-#define R_RISCV_GPREL_S 48
-#define R_RISCV_TPREL_I 49
-#define R_RISCV_TPREL_S 50
#define R_RISCV_RELAX 51
#define R_RISCV_SUB6 52
#define R_RISCV_SET6 53
@@ -4134,8 +4126,12 @@ enum
#define R_RISCV_PLT32 59
#define R_RISCV_SET_ULEB128 60
#define R_RISCV_SUB_ULEB128 61
+#define R_RISCV_TLSDESC_HI20 62
+#define R_RISCV_TLSDESC_LOAD_LO12 63
+#define R_RISCV_TLSDESC_ADD_LO12 64
+#define R_RISCV_TLSDESC_CALL 65
-#define R_RISCV_NUM 62
+#define R_RISCV_NUM 66
/* RISC-V specific values for the st_other field. */
#define STO_RISCV_VARIANT_CC 0x80 /* Function uses variant calling
@@ -4144,7 +4140,7 @@ enum
/* RISC-V specific values for the sh_type field. */
#define SHT_RISCV_ATTRIBUTES (SHT_LOPROC + 3)
-/* RISC-V specific values for the p_type field. */
+/* RISC-V specific values for the p_type field (deprecated). */
#define PT_RISCV_ATTRIBUTES (PT_LOPROC + 3)
/* RISC-V specific values for the d_tag field. */
--
2.56.0
